Motorola PowerQUICC II MPC8280 Series Reference Manual page 896

Programming the USB Host Controller (Packet-Level)
Initialization Example.")
• Set the host bit in the mode register (USBMOD[HOST] = 1) to configure the
controller as a host.
• Set the multi-frame bit in the endpoint configuration register (USEP1[MF] = 1) to
allow SETUP/OUT tokens and DATA0/DATA1 packets to be sent back-to-back.
• Prepare tokens in separate BDs.
• Using software, append the CRC5 as part of the transmitted data because the CPM
does not support automatic CRC5 generation.
• Clock the USB host controller as a high speed function (48-MHz reference clock).
• For low-speed transactions with an external hub, set TxBD[LSP] in the token's BD.
This causes the USB host controller to generate a preamble (PRE token) at full speed
before changing the transmit rate to low speed and sending the data packet. After
completion of the transaction, the host returns to full-speed operation. Note that LSP
should be set only for token BDs.
27.10.1 USB Host Controller Initialization Example
The following is a local loopback example initialization sequence for the USB controller
operating as a host. It can be used to set up the host endpoint and one function endpoint to
demonstrate an IN token transaction.
1. Program CMXSCR to provide a 48 MHz clock to the USB controller.
2. Program the Port Registers to select USBRXD, USBRXP, USBRXN, USBTXP,
USBTXN, and USBOE.
3. Write (DPRAM+0x500) to EP1PTR, (DPRAM+0x520) to EP2PTR to set up the
endpoint pointers.
4. Write 0x0000_0020 to DPRAM+0x500 to set up the RBASE and TBASE fields of
the host endpoint parameter RAM.
5. Write 0x1818_0100 to DPRAM+0x504 to set up the RFCR, TFCR, and MRBLR
fields of the host endpoint parameter RAM.
6. Write 0x0000_0020 to DPRAM+0x508 to set up the RBPTR and TBPTR fields of
the host endpoint parameter RAM.
7. Clear the TSTATE field of the host endpoint parameter RAM.
8. Write 0x0008_0028 to DPRAM+0x520 to set up the RBASE and TBASE fields of
the endpoint 2 parameter RAM.
9. Write 0x1818_0100 to DPRAM+0x524 to set up the RFCR, TFCR, and MRBLR
fields of the endpoint 2 parameter RAM.
10. Write 0x0008_0028 to DPRAM+0x528 to set up the RBPTR and TBPTR fields of
the endpoint 2 parameter RAM.
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MPC8280 PowerQUICC II Family Reference Manual
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