Motorola PowerQUICC II MPC8280 Series Reference Manual page 488

SDRAM Machine
11.4.9 SDRAM M
The MPC8280 transfers mode register data (CAS latency, burst length, burst type) stored
in P/LSDMR to the SDRAM array by issuing the
timing for the -
MODE SET
Mode Set
CLK
ALE
CS
SDRAS
SDCAS
*Mode Data
MA[0–11]
WE
DQM
Data
*The mode data is the address value during a mode-set cycle. It is driven by the memory controller, in single
MPC8280 mode, according to P/LSDMR[CL] register. In 60x-compatible mode, software must drive the correct
value on the address lines. Figure 11-38. shows the actual value.
Figure 11-37. SDRAM M
Figure 11-38 shows mode data bit settings.
Bit number 0 1
11.4.10 SDRAM Refresh
The memory controller supplies auto (CBR) refreshes to SDRAM according to the interval
specified in PSRT or LSRT. This represents the time period required between refreshes. The
value of P/LSRT depends on the specific SDRAM devices used and the operating
frequency of the MPC8280's bus. This value should allow for a potential collision between
memory accesses and refresh cycles. The period of the refresh interval must be greater than
the access time to ensure that read and write operations complete successfully.
11-50
Freescale Semiconductor, Inc.
-S Command Timing
ODE ET
command.
Page Activate
Row
Z
2 3 4 5 6
CL
latency mode—can be 1(001), 2(010), or 3(011).
Figure 11-38. Mode Data Bit Settings
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
- command. Figure 11-37 shows
MODE SET
Write (Burst)
Column
D0 D1 D2
-S Command Timing
ODE ET
7 8 9 10 11
0 BL
burst length:
4(010) for 16- and 64-bit port sizes
8(011) for 8- and 32-bit port sizes
D3
Z
lsb
MOTOROLA