Motorola PowerQUICC II MPC8280 Series Reference Manual page 1118

Configuring the ATM Controller for Maximum CPM Performance
SN field equals 1, 3, 5, and 7 and writes the result to external SRTS logic, as shown in
Figure 31-69.
Figure 31-69. AAL1 CES SRTS Clock Recovery Using External Logic
On every eighth cell, the MPC8280 writes a new SRTS code to the external logic using the
bus selected in RCT[BIB]. The CP writes the SRTS code using a DMA write cycle of
1-byte data size. Each AAL1 CES channel can be programmed to select one of 16 addresses
available for writing the SRTS result. The SRTS code is written to the least-significant
nibble of that address (SRTS[0]=lsb, SRTS[3]=msb). The SRTS is synchronized with the
sequence count cycle—SRTS[3] is read from the cell with SN = 1 and SRTS[0] is read from
the cell with SN = 7. The SRTS PLL makes periodic clock adjustments based on the
difference between a locally generated SRTS and a remotely generated SRTS retrieved
every eight received cells.
31.17 Configuring the ATM Controller for Maximum
CPM Performance
The following sections recommend ATM controller configurations to maximize CPM
performance.
31.17.1 Using Transmit Internal Rate Mode
When the total transmit rate is less than the PHY rate, use the transmit internal rate mode
and configure the internal rate clock to the maximum bit rate required. (See 31.2.1.5,
"Transmit External Rate and Internal Rate Modes.") The PHY then automatically fills the
unused bandwidth with idle cells, not the ATM controller. If the internal rate mode is not
31-104
Freescale Semiconductor, Inc.
External SRTS Logic
(N=3008 bits = 8 SAR PDU)
fs
Counter
divided by N
2.43 MHz (E1/T1)
155.52 MHz
1/64
VCO
DMA writes new SRTS code
SN=1
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SRTS
Latch
p = 4 bit
counter
+
SRTS Diff
-
Latch
SN=3 SN=5 SN=7
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