Motorola PowerQUICC II MPC8280 Series Reference Manual page 993

Receive
Modem Lines
Control
RXD
Decoder
Delimiter
Table 30-1. Internal Clocks to CPM Clock Frequency Ratio
Mode
HDLC 1 bit
Transparent 1 bit
HDLC nibble
Fast Ethernet
ATM
30.2 General FCC Mode Registers (GFMRx)
Each FCC contains a general FCC mode register (GFMRx) that defines common FCC
options and selects the protocol to be run. The GFMRx are read/write registers cleared at
reset. Figure 30-2 shows the GFMR format.
MOTOROLA Chapter 30. Fast Communications Controllers (FCCs)
Freescale Semiconductor, Inc.
60x Bus
Control
Registers
Peripheral Bus
Receive
Data
FIFO
Unit
Shifter
Figure 30-1. FCC Block Diagram
Internal Clock: CPM clock frequency ratio
1:4
1:4
1:6
1:3 (1:3.5 preferred)
1:3 (1:3.5 preferred)
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Go to: www.freescale.com
General FCC Mode Registers (GFMRx)
Clock
Generator
Internal Clocks
Transmit
Data
FIFO
Transmit
Control
Unit
Shifter Delimiter
TCLK
RCLK
Modem Lines
TXD
Encoder
30-3