Motorola PowerQUICC II MPC8280 Series Reference Manual page 1369

0
Field —
Reset
R/W
Addr
Figure 39-7. SPIE/SPIM—SPI Event/Mask Registers
Table 39-3 describes the SPIE/SPIM fields.
Bits Name
0–1 — Reserved, should be cleared.
2 MME Multimaster error. Set when SPISEL is asserted externally while the SPI is in master mode.
3 TXE Tx error. Set when an error occurs during transmission.This event is not maskable via the TxBD[I] bit.
4 — Reserved, should be cleared.
5 BSY Busy. Set after the first character is received but discarded because no Rx buffer is available.
6 TXB Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Wait two
character times to be sure data is completely sent over the transmit signal.
7 RXB Rx buffer. Set after the last character is written to the Rx buffer and the BD is closed.
39.4.3 SPI Command Register (SPCOM)
The SPI command register (SPCOM), shown in Figure 39-8, is used to start SPI operation.
0
Field STR
Reset
R/W
Addr
Figure 39-8. SPCOM—SPI Command Register
Table 39-4 describes the SPCOM fields.
Bits Name
0 STR Start transmit. For an SPI master, setting STR causes the SPI to start transferring data to and from
the Tx/Rx buffers if they are prepared. For a slave, setting STR when the SPI is idle causes it to load
the Tx data register from the SPI Tx buffer and start sending with the next SPICLK after SPISEL is
asserted. STR is cleared automatically after one system clock cycle.
1–7 — Reserved and should be cleared.
MOTOROLA
Freescale Semiconductor, Inc.
1 2 3
MME TXE
0x11AA6 (SPIE); 0x11AAA (SPIM)
Table 39-3. SPIE/SPIM Field Descriptions
1
Table 39-4. SPCOM Field Descriptions
Chapter 39. Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
Programming the SPI Registers
4 5
— BSY
0000_0000
R/W
Description
—
0000_0000
Write Only
0x11AAD
Description
6 7
TXB RXB
7
39-11