Motorola PowerQUICC II MPC8280 Series Reference Manual page 1301

The scrambling function is performed on the ATM cell payload if TCMODEx[TPS] = 1.
The ATM cell header HEC value is calculated and the coset function is performed on the
HEC if TCMODEx[TC] = 1. The ATM cell is then sent to the PHY via the SI. Once ATM
cell transmission is complete, the relevant TC layer cell counters are updated.
When a TC layer cell counter overflows, an interrupt (TCERx[TOF]) is set (if enabled in
the corresponding TCMRx[TOF]).
The TC layer is responsible for providing the data rate required by the physical medium
device (PMD). On MPC8280 there are two ATM transmit modes. Users should refer to
Section 31.2.1.5, "Transmit External Rate and Internal Rate Modes," for more details. The
following text and figures are specific to TC layer operation.
• External Rate—In general, the TC would never have its transmit FIFO empty, and
thus would not need to generate idle cells. However, if the CPM is busy and if the
transmit FIFO is empty, the TC layer generates an idle cell and an underrun
condition will occur. If TCMODEx[URE] = 1, the TCERx[UR] interrupt is sent to
the host (if not masked). See Figure 35-10.
.
MPC8280
2M Serial Rate
PHY
Idle Cell
ATM Cell
Figure 35-10. TC Operation in FCC External Rate Mode
• Internal Rate (Sub Rate)—The TC layer continues to request ATM cells and
transmits idle cells. TCERx[UR] interrupts can by disabled by clearing
TCMODEx[URE] until a valid ATM cell is transmitted via the internal UTOPIA bus
from FCC2 to the TC layer FIFO. See Figure 35-11.
MOTOROLA
Freescale Semiconductor, Inc.
2M Cell Rate
UTOPIA
TC
Chapter 35. ATM Transmission Convergence Layer
For More Information On This Product,
Go to: www.freescale.com
TC Layer Programming Mode
Keep FCC FIFO full
CP
Generate Idle Cells
cell_req
BTM
FCC
(External Rate)
ATM Channels
DPR
35-15