Motorola PowerQUICC II MPC8280 Series Reference Manual page 1104

The UTOPIA Interface
Table 31-45. UTOPIA Slave Mode Signals (continued)
Signal
TxCLK Transmit clock. Provides the synchronization reference for the TxDATA, TxSOC, TxENB,
TxCLAV, and TxPRTY signals. All of the above signals are sampled at low-to-high transitions of
TxCLK.
TxADD[4–0] Transmit address. Address bus from the master to the ATM controller used to select the
appropriate M-PHY device.
RxDATA[15–0]/[7–0] Receive data bus. Carries receive data from the master to the ATM controller. RxDATA[15]/[7]
is the msb, RxDATA[0] is the lsb.
RxSOC Receive start of cell. Asserted by the master device whenever the first byte of a cell is being
received on the RxDATA lines.
RxENB Receive enable. Asserted by the master device to signal the slave to sample the RxDATA and
RxSOC signals.
RxCLAV Receive cell available. Asserted by the ATM controller to indicate it can receive a complete cell.
RxPRTY Receive parity. Asserted by the PHY device. It is an odd parity bit over the RxDATA[15–0]. If
there is a RxPRTY error and the receive parity check FPSMR[RxP] is cleared, the cell is
discarded. See Section 31.13.2, "FCC Protocol-Specific Mode Register (FPSMR)," and
Section 31.10.7, "UNI Statistics Table."
RxCLK Receive clock. Provides the synchronization reference for the RxDATA, RxSOC, RxENB,
RxCLAV, and RxPRTY signals. All the above signals are sampled at low-to-high transitions of
RxCLK.
RxADD[4–0] Receive address. Address bus from master to the ATM controller device used to select the
appropriate M-PHY device.
31.12.2.1 UTOPIA Slave Multiple PHY Operation
The user should write the ATM controller PHY address in FPSMR[PHY ID].
31.12.2.2 UTOPIA Clocking Modes
The UTOPIA clock can be generated internally or externally. If the UTOPIA clock is to be
generated internally, the user should assign one of the baud-rate generators to supply the
UTOPIA clock. See Chapter 16, "CPM Multiplexing."
31.12.2.3 UTOPIA Loop-Back Modes
The UTOPIA interface supports loop-back mode. In this mode, the Rx and Tx UTOPIA
signals are shorted internally. Output pins are driven; input pins are ignored.
Note that in loop-back mode, the transmitter and receiver must operate in complementary
modes. For example, if the transmitter is master, the receiver must be a slave
(FPSMR[TUMS] = 0, FPSMR[RUMS] = 1).
31-90
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MPC8280 PowerQUICC II Family Reference Manual
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