Motorola PowerQUICC II MPC8280 Series Reference Manual page 525

MPC8280
BS[0–7]
BCTL0
A[19–28]
D[0–63]
Figure 11-67. DRAM Interface Connection to the 60x Bus (64-Bit Port Size)
After timings are created, programming the UPM continues with translating these timings
into tables representing the RAM array contents for each possible cycle. When a table is
completed, the global parameters of the UPM must be defined for handling the disable
timer (precharge) and the refresh timer relative to Figure 11-67. Table 11-42 shows settings
of different fields.
Machine select UPMA
Port size 64-bit
No write protect (R/W)
Refresh timer value (1024 refresh cycles)
Refresh timer enable
Address multiplex size
Disable timer period
Select between GPL4 and UPMWAIT = GPL4 data sample at clock rising edge
Burst inhibit device
The OR and BR of the specific bank must be initialized according to the address mapping
of the DRAM device used. The MS field should indicate the specific UPM selected to
handle the cycle. The RAM array of the UPM can than be written through use of the
MOTOROLA
Freescale Semiconductor, Inc.
CS1
Table 11-42. UPMs Attributes Example
Explanation
Chapter 11. Memory Controller
For More Information On This Product,
Go to: www.freescale.com
Memory System Interface Example Using UPM
1M x 16
RAS
CAS[0–1]
W
A[0–9]
D[0–15]
16
16
D[0–15]
RAS
CAS[0–1]
W
A[0–9]
1M x 16
PURT[PURT]
MxMR[RFEN]
MxMR[AMx]
MxMR[DSx]
MxMR[GPL_x4DIS]
1M x 16
RAS
CAS[0–1]
W
A[0–9]
D[0–15
16
16
D[0–15]
RAS
CAS[0–1]
W
A[0–9]
1M x 16
Field Value
BRx[MS] 0b100
BRx[PS] 0b00
BRx[WP] 0b0
0x0C
0b1
0b010
0b01
0b0
ORx[BI] 0b0
11-87