Motorola PowerQUICC II MPC8280 Series Reference Manual page 1327

Error
Non-octet error The Ethernet controller handles a nibble of dribbling bits when the receive frame terminates as
(dribbling bits) nonoctet aligned and it checks the CRC of the frame on the last octet boundary. If there is a CRC
error, the frame nonoctet aligned (RxBD[NO]) error is reported, FCCE[RXF] is set, and the alignment
error counter (ALEC) in the parameter RAM is incremented. If there is no CRC error, no error is
reported.
CRC error When a CRC error occurs, the controller closes the buffer, and sets RxBD[CR] and FCCE[RXF].
Also, the CRC error counter (CRCEC) in the parameter RAM is incremented. After receiving a frame
with a CRC error, the receiver enters hunt mode. CRC checking cannot be disabled, but the CRC
error can be ignored if checking is not required.
36.18 Fast Ethernet Registers
The following sections describe registers used for configuring and operating the Fast
Ethernet controller.
36.18.1 FCC Ethernet Mode Registers (FPSMRx)
The MPC2880 supports 10/100 Mbps Ethernet through a RMII interface (according to
RMII Specification March 20, 1998). The RMII use a single reference clock (50 MHz) and
seven pins which are a proper subset of the MII interface pins. Ethernet features are
unchanged in RMII mode. To select RMII-PHY interface, a mode bit in the Ethernet mode
register (FPSMR) has been added, as shown in Figure 36-6.
0 1 2
Field HBC FC SBT
Reset
R/W
Addr
16
Field —
Reset
R/W
Addr
Figure 36-6. FCC Ethernet Mode Registers (FPSMRx)
MOTOROLA
Freescale Semiconductor, Inc.
Table 36-7. Reception Errors (continued)
3 4 5 6
LPB LCW FDE MON
0000_0000_0000_0000
0x11304 (FPSMR1), 0x11324 (FPSMR2)
20 21 22
CAM BRO
0000_0000_0000_0000
0x11306 (FPSMR1), 0x11326 (FPSMR2)
Chapter 36. Fast Ethernet Controller
For More Information On This Product,
Go to: www.freescale.com
Description
7 8 9 10 11
— PRO FCE RSH
R/W
23 24 25 26
— CRC
R/W
Fast Ethernet Registers
12 13 14 15
— RMII —
31
—
36-21