Motorola PowerQUICC II MPC8280 Series Reference Manual page 1388

2
I C Parameter RAM
a user-programmed pointer (I2C_BASE) located in the parameter RAM; see
Section 14.5.2, "Parameter RAM." The I
aligned address in the dual-port RAM's general-purpose area (banks 1–8, 11 and 12). The
user must initialize certain parameter RAM values before the I
initializes the other values. Software usually does not access parameter RAM entries once
they are initialized; they should be changed only when the I
Table 40-6 shows the I
Table 40-6. I
1
Offset Name Width
0x00 RBASE Hword Rx/TxBD table base address. Indicate where the BD tables begin in the dual-port RAM.
0x02 TBASE Hword
0x04 RFCR Byte Rx/Tx function code registers. The function code registers contain the transaction
0x05 TFCR Byte
0x06 MRBLR Hword Maximum receive buffer length. Defines the maximum number of bytes the MPC8280
0x08 RSTATE Word Rx internal state.
0x0C RPTR Word Rx internal data pointer
0x10 RBPTR Hword RxBD pointer. Points to the next descriptor the receiver transfers data to when it is in an
0x12 RCOUNT Hword Rx internal byte count
0x14 RTEMP Word Rx temp.
0x18 TSTATE Word Tx internal state.
0x1C TPTR Word Tx internal data pointer
40-10
Freescale Semiconductor, Inc.
2 C parameter table can be placed at any 64-byte
2
C parameter memory map.
2
C Parameter RAM Memory Map
Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs are
allocated for the Tx and Rx sections of the I
2
the I C. Furthermore, do not configure BD tables of the I
controller's parameter RAM. RBASE and TBASE should be divisible by eight.
specification associated with SDMA channel accesses to external memory. See
Figure 40-11 and Table 40-7.
writes to a Rx buffer before moving to the next buffer. The MPC8280 writes fewer bytes
to the buffer than the MRBLR value if an error or end-of-frame occurs. Buffers should
not be smaller than MRBLR.
Tx buffers are unaffected by MRBLR and can vary in length; the number of bytes to be
sent is specified in TxBD[Data Length].
MRBLR is not intended to be changed while the I
changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles
back-to-back). The change takes effect when the CP moves control to the next RxBD.
To guarantee the exact RxBD on which the change occurs, change MRBLR only while
2
the I C receiver is disabled. MRBLR should be greater than zero; it should be an even
number if the character length of the data exceeds 8 bits.
2
Reserved for CP use.
2
is updated by the SDMA channels to show the next address in
the buffer to be accessed.
idle state or to the current descriptor during frame processing for each I
After a reset or when the end of the descriptor table is reached, the CP initializes
RBPTR to the value in RBASE. Most applications should not write RBPTR, but it can
be modified when the receiver is disabled or when no receive buffer is used.
2
is a down-count value that is initialized with the MRBLR value
and decremented with every byte the SDMA channels write.
2
Reserved for CP use.
2
Reserved for CP use.
2
in the buffer to be accessed.
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2 C is inactive.
Description
2
C. Initialize RBASE/TBASE before enabling
2
C is operating. However it can be
is updated by the SDMA channels to show the next address
2
C is enabled; the CP
2
C to overlap any other active
2
C channel.
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