Motorola PowerQUICC II MPC8280 Series Reference Manual page 1283

3. Make this the active ICP template (see Section 34.5.4.1, "Transmit ICP Cell
Signalling").
4. Repeat steps 1-3 until the test is inactive.
There are two ways to monitor the link under test. The first method is to simply look for the
expected LID in the received ICP cells (ICP cell buffer). For this to happen, all links in the
group must have MON_ICP bit set:
1. Monitor link for changes in SCCI: ILRCNTL[MON_ICP] = 1.
Now, since changed ICP cells are passed to the ICP buffer only when the SCCI field
changes, then it may take some time for the link under test to pass on an ICP cell. Again,
ICP cells will be passed on to the buffer for the first link encountered in which a change
(SCCI) is detected, it may or may not be the link under test. An alternate method is to
monitor only the link under test:
1. Don't Monitor link for changes in SCCI for all links except link under test:
ILRCNTL[MON_ICP] = 0 (alter the corresponding Link Table Entries).
2. Monitor link under test for changes in SCCI: ILRCNTL[MON_ICP] = 1.
This will allow only changed ICP cells for the link under test to be passed on to the ICP
Cell buffer.
34.5.4.12 IDCR Operation
The ATM stream reconstruction (RX) can be driven alternatively by another clock source
(as opposed to triggered by the arrival of cells/CLAV). The reconstruction rate (IMA Data
Cell Rate (IDCR)) clock can be generated by an external clock or by one of the MPC8280's
baud rate generators (BRGs). Note that the designated Rx TRL is used to record the TRLR
(TRL Rate) and this is only captured once, when a group's GDS process is initialized. After,
GDS is completed, the TRLR cannot be updated (unless the group is re-initialized.
34.5.4.12.1 IDCR Start-up
There are some basic initialization steps that must be performed before any of the groups
are activated and make use of IDCR stream reconstruction. These steps should only be
performed once:
1. Configure the base offset of the IDCR Table in the IMA Root table:
IMAROOT[IDCR_BASE] = x.
2. Reset (to zero) the IDCR tick counter: IMAROOT[IDCRTICK] = 0.
3. Reset (to zero) the IDCR in Service field: IMAROOT[IDCR_SVC] = 0.
4. Reset (to zero) the IDCR_EN field: IMAROOT[IDCREN] = 0. Subsequently, any
groups operating in IDCR mode will require that this field be updated (ORed) to
enable IDCR mode (e.g. set bit for the corresponding group).
MOTOROLA
Freescale Semiconductor, Inc.
Chapter 34. Inverse Multiplexing for ATM (IMA)
For More Information On This Product,
Go to: www.freescale.com
IMA Software Interface and Requirements
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