Motorola PowerQUICC II MPC8280 Series Reference Manual page 1423

Glossary of Terms and Abbreviations
The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this
book. Some of the terms and definitions included in the glossary are reprinted from IEEE
Std. 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, copyright ©1985 by
the Institute of Electrical and Electronics Engineers, Inc. with the permission of the IEEE.
Note that some terms are defined in the context usage in this book.
A
Architecture. A detailed specification of requirements for a processor or
Asynchronous exception. Exception caused by events external to the
Atomic access. A bus access that attempts to be part of a read-write operation
Autobaud. The process of determining a serial data rate by timing the width
B
Big-endian. A byte-ordering method in memory where the address n of a
Blockage. A pipeline stall that occurs when an instruction occupies an
Boundedly undefined. A characteristic of results of certain operations that
MOTOROLA
Freescale Semiconductor, Inc.
computer system. It does not specify details for implementing the
processor or computer system; instead, it provides a template for a
family of compatible implementations.
processor's execution. In this document, the term 'asynchronous
exception' is used interchangeably with the word 'interrupt'.
to the same address uninterrupted by any other access to that address
(the term refers to the fact that the transactions are indivisible). The
PowerPC architecture implements atomic accesses through the
lwarx/stwcx. instruction pair.
of a single bit.
word corresponds to the most-significant byte. In an addressed
memory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0
as the most-significant byte. See Little-endian.
execution unit and prevents a subsequent instruction from being
dispatched.
are not rigidly prescribed by the PowerPC architecture. Boundedly-
Glossary of Terms and Abbreviations
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