Motorola PowerQUICC II MPC8280 Series Reference Manual page 1021

31.2.1.3 AAL0 Transmitter Overview
No specific adaptation layer is provided for AAL0. The ATM controller reads a whole cell
from an external buffer, which always contains exactly one AAL0 cell. The ATM controller
optionally generates CRC10 on the cell payload and places it at the end of the payload
(CRC10 field). AAL0 mode can be used to send OAM cells or AAL3/4 raw cells.
31.2.1.4 AAL2 Transmitter Overview
Refer to Section 33.3.1, "Transmitter Overview."
31.2.1.5 Transmit External Rate and Internal Rate Modes
The ATM controller supports the following two rate modes:
• External rate mode—The total transmission rate is determined by the PHY
transmission rate. The FCC sends cells to keep the PHY FIFOs full; the FCC inserts
idle/unassign cells to maintain the transmission rate.
• Internal rate mode—The total transmission rate is determined by the FCC internal
rate timers. In this mode, the FCC does not insert idle/unassign cells. The internal
rate mechanism supports up to 4 different rates. Each PHY has its own FTIRR,
described in Section 31.15.1.1, "FCC Transmit Internal Rate Register (FTIRRx)."
The FTIRR includes the initial value of the internal rate timer. A cell transmit
request is sent when an internal rate timer expires. When using internal rate mode,
the user assigns one of the baud-rate generators (BRGs) to clock the four internal
rate timers.
31.2.2 Receiver Overview
Before the receiver is enabled, the host must initialize the MPC8280 and create the receive
data structure described in Section 31.10, "ATM Memory Structure." The host arranges a
BD table for each ATM channel. Buffers for each connection can be statically allocated
(that is, each BD in the BD table is associated with a fixed buffer location) or in the case of
AAL5, can be fetched by the CP from a global free buffer pool. See Section 31.10.5, "ATM
Controller Buffer Descriptors (BDs)."
The receiver ATM cell size is 53–65 bytes. The cell includes: 4 bytes ATM cell header, 1
byte HEC, which can be checked by setting FPSMR[HECC] (refer to Table 31-47), and 48
bytes payload. User-defined cells (UDC mode) include an extra header of 1–12 bytes with
an optional HEC octet. Cell transfers use the UTOPIA level II, cell-level handshake.
Reception starts when the PHY asserts the receive cell available signal (RxCLAV) to
indicate that the PHY has a complete cell in its receive FIFO. The receiver reads a complete
cell from the UTOPIA interface and translates the header address (VP/VC) to a channel
code by performing an address look-up. If no matches are found, the cell is discarded and
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
Freescale Semiconductor, Inc.
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ATM Controller Overview
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