Motorola PowerQUICC II MPC8280 Series Reference Manual page 1389

Table 40-6. I
1
Offset Name Width
0x20 TBPTR Hword TxBD pointer. Points to the next descriptor that the transmitter transfers data from when
0x22 TCOUNT Hword Tx internal byte count
0x24 TTEMP Word Tx temp.
0x34 SDMATMP Word SDMA temp.
1
From the pointer value programmed in I2C_BASE at IMMR + 0x8AFC.
2
Normally, these parameters need not be accessed.
Figure 40-11 shows the RFCR/TFCR bit fields.
0
Field
Reset
R/W
Addr
Figure 40-11. I
Table 40-7 describes the RFCR/TFCR bit fields.
Bits Name
0–1 — Reserved, should be cleared.
2 GBL Global access bit
0 Disable memory snooping
0 Enable memory snooping
3–4 BO Byte ordering. Selects the required byte ordering for the buffer. If BO is changed on-the-fly, it takes
effect at the beginning of the next frame or BD.
00 True little-endian. Note this mode can only be used with 32-bit port size memory.
01 Big-endian
1x Munged little-endian
5 TC2 Transfer code 2. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
6 DTB Data bus indicator.
0 Use 60x bus for SDMA operation.
1 Use local bus for SDMA operation.
7 — Reserved, should be cleared.
MOTOROLA
Freescale Semiconductor, Inc.
2
C Parameter RAM Memory Map (continued)
it is in an idle state or to the current descriptor during frame transmission. After a reset
or when the end of the descriptor table is reached, the CP initializes TBPTR to the value
in TBASE.Most applications should not write TBPTR, but it can be modified when the
transmitter is disabled or when no transmit buffer is used.
2
is a down-count value initialized with TxBD[Data Length] and
decremented with every byte read by the SDMA channels.
2
Reserved for CP use.
2
Reserved for CP use.
1 2 3
GBL
I2C_BASE + 04 (RFCR)/I2C_BASE + 05 (TFCR)
2
C Function Code Registers (RFCR/TFCR)
Table 40-7. RFCR/TFCR Field Descriptions
Chapter 40. I
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Description
4 5
BO TC2
0000_0000
R/W
Description
2
C Controller
2
I C Parameter RAM
6 7
DTB —
40-11