Motorola PowerQUICC II MPC8280 Series Reference Manual page 1082

ATM Memory Structure
Table 31-29. APC Parameter Table (continued)
1
Offset Name
0x0A LINE_RATE_ABR Hword ABR only. The PHY line rate in cells/sec, represented in TM 4.0 floating-point
0xC REAL_TSTP
0x10 APC_STATE
1 Offset values are to APCP_BASE+PHY# × 32. However, in slave mode, the offset is from APCP_BASE regardless
of the PHY address.
31.10.4.2 APC Priority Table
Each PHY's APC priority table holds pointers to the APC scheduling table of each priority
level. It resides in the dual-port RAM. The priority table can hold up to eight priority levels.
Table 31-30 shows the structure of a priority table entry.
Offset Name
0x00 APC_LEVi_BASE Hword APC level i base address. Pointer to the first slot in the APC scheduling table for
0x02 APC_LEVi_END Hword APC level i end address. Pointer to the last slot in the APC scheduling table for
0x04 APC_LEVi_RPTR Hword APC level i real-time/service pointers. APC table pointers used internally by the
0x06 APC_LEVi_SPTR Hword
31.10.4.3 APC Scheduling Tables
The APC uses APC scheduling tables (one table for each priority level) to schedule channel
transmission. A scheduling table is divided into time slots, as shown in Figure 31-39. Each
slot is a half-word entry. Note that the APC scheduling tables should be cleared before the
APC unit is enabled.
APC_LEVi_BASE
Figure 31-39. The APC Scheduling Table Structure
31-68
Freescale Semiconductor, Inc.
Width
format. User-defined.
Word Real-time stamp pointer used internally by the APC. Should be cleared initially.
Word Used internally by the APC. Should be cleared initially.
Table 31-30. APC Priority Table Entry
Width
level i. Should be half-word aligned. User-defined.
level i. Should be half-word aligned. User-defined.
APC. Initialize both pointers to APC_LEVi_BASE.
slot 0 slot 1
Half Word Entry
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Description
Description
Control
slot N
Slot
APC_LEVi_END
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