Motorola PowerQUICC II MPC8280 Series Reference Manual page 1201

0
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0c
Offset + 0x0e
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
Offset + 0x1A
Offset + 0x1C
Offset + 0x1E
Table 33-11 describes the SSSAR RxQD fields.
.
Table 33-11. SSSAR RxQD Field Descriptions
1
Offset Bits Name
0x00 0–10 —
11 RasT
12 RBM
13 RFM
14-15 SubType
MOTOROLA
Freescale Semiconductor, Inc.
—
Max_SSSAR_SDU_Length
Figure 33-20. SSSAR Rx Queue Descriptor
Reserved, should be cleared during initialization.
Ras Timer enable.
0 Ras Timer disabled (Time Stamp field is still valid)
1 Ras Timer enabled. The Ras Timer duration is set by the Ras Timer Duration
parameter in the parameter RAM. If the current SSSAR SDU is not completed
before the RasTimer expires, the BD is closed showing the Ras_Timer expired (TE)
(SSSAR RxBD[RxError] = 01) and the next packet starts a new SDU.
Receive buffer mask.
0 Disable receive buffer interrupt
1 Enable receive buffer interrupt
Receive frame mask.
0 Disable receive frame interrupt
1 Enable receive frame interrupt
Sublayer type. Should be 10 (SSSAR) for this descriptor.
00 CPS sublayer
01 CPS switched
10 SSSAR
11 Reserved
Chapter 33. ATM AAL2
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10 11
RasT
RxBD Table Offset
RxBD Table Base
—
Time Stamp
—
—
MRBLR
—
Description
AAL2 Receiver
12 13 14 15
RBM RFM SubType
33-33