Motorola PowerQUICC II MPC8280 Series Reference Manual page 555

In ECC/parity mode the L2 cache can support memory regions with ECC/Parity under the
following restrictions:
• All non-write-protected (BRx[WP] = 0) memory banks marked caching-allowed
must use either ECC (BRx[DECC] = 0b11) or read-modify-write parity
(BRx[DECC] = 0b10). See Section 11.3.1, "Base Registers (BRx)," for more
information about the MPC8280 base register parameters.
• Only PowerQUICC II-type masters are supported in systems that use ECC/parity L2
cache mode. See Section 11.9, "External Master Support (60x-Compatible Mode),"
for more information about external master types.
Figure 12-3. shows a MPC8280 connected to an MPC2605 integrated L2 cache in
ECC/Parity mode.
MOTOROLA
Freescale Semiconductor, Inc.
Chapter 12. Secondary (L2) Cache Support
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L2 Cache Configurations
12-5