Motorola PowerQUICC II MPC8280 Series Reference Manual page 1070

ATM Memory Structure
Offset Bits Name
0x00 0–1 —
2 GBL
3–4 BO
5 —
6 DTB
7 BIB
8 AVCF
9 —
10–11 ATT
12 CPUU
13 VCON
14–15 INTQ
31-56
Freescale Semiconductor, Inc.
Table 31-21. TCT Field Descriptions
Reserved, should be cleared.
Global. Asserting GBL enables snooping of data buffers, BDs, interrupt queues and free
buffer pool.
Byte ordering. This field is used for data buffers.
00 Reserved
01 Power PC little endian
1x Big endian
Reserved, should be cleared.
Data buffer bus
0 Reside on the 60x bus.
1 Reside on the local bus.
BD, interrupt queue and external SRTS logic bus
0 Reside on the 60xbus.
1 Reside on the local bus.
Note: When using AAL5, AAL1 CES in UDC mode, BDs and data should be placed on
the same bus (TCT[DTB]=TCT[BIB]).
Auto VC off. Determines the behavior of the APC when the last buffer associated with
this VC has been sent and no more ready buffers are in the VC's TxBD table.
0 The APC does not remove this VC from the schedule table and continues to schedule
it to transmit.
1 The APC removes this VC from the schedule table. To continue transmission after the
host adds buffers for transmission, a new
can be issued only after the CP clears TCT[VCON].
Note: When over-subscribing UBR or UBR+ channels, set AVCF so that the CPM does
not become overloaded polling non-active VCs.
Reserved, should be cleared.
ATM traffic type
00 Peak cell-rate pacing. The host must initialize PCR and the PCR fraction. Other traffic
parameters are not used.
01 Peak and sustain cell rate pacing (VBR traffic). The APC performs a continuous-state
leaky bucket algorithm (GCRA) to pace the channel-sustain cell rate. The host must
initialize PCR, PCR fraction, SCR, SCR fraction, and BT (burst tolerance).
10 Peak and minimum cell rate pacing (UBR+ traffic). The host must initialize PCR, PCR
fraction, MCR, MCR fraction, and MDA.
11 Reserved
CPCS-UU+CPI insertion (used for AAL5 only).
0 CPCS-UU+CPI insertion disabled. The transmitter clears the CPCS-UU+CPI fields.
1 CPCS-UU+CPI insertion enabled. The transmitter reads the CPCS-UU+CPI (16-bit
entry) from external memory. It should be placed after the end of the last buffer (it
should not be included in the buffer length).
Virtual channel is on.
Should be set by the host before it issues an
sets TCT[STPT] (stop transmit), the CP deactivates this channel and clears VCON when
the channel is next encountered in the APC scheduling table. The host can issue another
command only after the CP clears VCON.
ATM TRANSMIT
Points to one of four interrupt queues available.
MPC8280 PowerQUICC II Family Reference Manual
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Description
command is needed, which
ATM TRANSMIT
command. When the host
ATM TRANSMIT
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