Motorola PowerQUICC II MPC8280 Series Reference Manual page 528

Memory System Interface Example Using UPM
CLKIN
A
Row
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
cst1 0
cst2 0
cst3 0
cst4 0
bst1 1
bst2 1
bst3 1
bst4 1
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop 0
exen 0
amx0 1
amx1 0
na 0
uta 0
todt 0
last 0
RBS
Figure 11-70. Burst Read Access to FPM DRAM (No LOOP)
11-90
Freescale Semiconductor, Inc.
Column 1 Column 2
0 0 0
0 0 0
0 0 0
0 0 0
1 0 1
1 0 1
1 0 1
0 0 0
0 0 0
0 1 0
0 0 0
0 0 0
0 1 0
0 1 0
0 0 0
0 0 0
RBS+1 RBS+2 RBS+3
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Column 3 Column 4
0 0 0
0 0 0
0 0 0
0 0 0
0 1 0
0 1 0
0 1 0
0 0 0
0 0 0
1 0 1
0 0 0
0 0 0
1 0 1
1 0 1
0 0 0
0 0 0
RBS+4 RBS+5 RBS+6 RBS+7
0 0 Bit 0
0 0 Bit 1
0 0 Bit 2
0 1 Bit 3
1 0 Bit 4
1 0 Bit 5
1 0 Bit 6
0 0 Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
0 0 Bit 24
0 0 Bit 25
0 0 Bit 26
0 0 Bit 27
0 0 Bit 28
0 1 Bit 29
0 1 Bit 30
0 1 Bit 31
RBS+8
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