Motorola PowerQUICC II MPC8280 Series Reference Manual page 1442

slave, 39-19
programming model, 39-7
RxBD, 39-16
slave mode, 39-5
SPCOM, 39-11
SPIE, 39-10
SPIM, 39-10
SPMODE, 39-7
TxBD, 39-17
system interface unit (SIU)
60x bus monitor function, 4-3
add flexibility to CPM interrupt priorities, 4-13
BCR, 4-27
block diagram, 4-2
bus monitor, 4-4
clocks, 4-4
configuration functions, 4-2
configuration/protection logic block diagram, 4-3
encoding the interrupt vector, 4-15
FCC relative priority, 4-13
flexibility of interrupt priorities, 4-13
highest priority interrupt, 4-14
IMMR, 4-37
interrupt controller features list, 4-8
interrupt priorities, add flexibility, 4-13
interrupt source priorities, 4-11
interrupt vector calculation, 4-15
interrupt vector encoding, 4-15
interrupt vector generation, 4-15
L_TESCR1, 4-43
L_TESCR2, 4-44
LCL_ACR, 4-32
LCL_ALRH, 4-33
LCL_ALRL, 4-34
local bus monitor function, 4-3
masking interrupt sources, 4-14
MCC relative priority, 4-13
periodic interrupt timer (PIT), 4-5
periodic interrupt timer (PIT) function, 4-3
pin multiplexing, 4-51
PISCR, 4-47
PITC, 4-48
PITR, 4-49
port C interrupts, 4-17
PPC_ACR, 4-30
PPC_ALRH, 4-31
PPC_ALRL, 4-32
programming model, 4-18
registers, 4-18
SCC relative priority, 4-13
SCPRR_H, 4-20
SCPRR_L, 4-21
SICR, 4-18
SIEXR, 4-26
Index-8
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signal multiplexing, 4-51
SIMR_H, 4-23
SIMR_L, 4-24
SIPNR_H, 4-22
SIPNR_L, 4-23
SIPRR, 4-19
SIUMCR, 4-34
SIVEC, 4-25
software watchdog timer, 4-6
SWR, 4-8
SWSR, 4-39
SYPCR, 4-38
system protection, 4-2
TESCR1, 4-40
TESCR2, 4-42
time counter (TMCNT)
function, 4-3
overview, 4-5
timers, 4-4
TMCNT, 4-45
TMCNTAL, 4-46
TMCNTSC, 4-45
timers
memory map, 3-9
Completion unit, 2-8
Conventions
notational conventions, lxxxvi, II-1, III-2, IV-4
terminology, xc
see G2_LE core
Core, , 2-1
CPCR (CP command register), 14-12
CPCR (CPM command register), 27-34
CPM multiplexing logic (CMX)
overview, 16-1
see also Serial interface (SI)
CPM multiplexing, see CPM multiplexing logic
(CMX)
CPM MUX memory map, 3-22
CPM MUX, see CPM multiplexing logic (CMX)
CxTx (chip-select signals), 11-78
D
DCM (IDMA channel mode), 19-20
Digital phase-locked loop (DPLL) operation, 20-22
Dispatch unit, 2-6
DSR (data synchronization register)
overview, 20-9
UART mode, 21-11
Dual-port RAM
buffer descriptors, 14-22
parameter RAM, 14-23
E
EAMUX (external address multiplexing) signal, 11-45
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