Motorola PowerQUICC II MPC8280 Series Reference Manual page 929

Table 28-13. SMC Transparent RxBD Field Descriptions (continued)
Bits Name
2 W Wrap (last BD in RxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that
RBASE points to. The number of RxBDs is determined only by the W bit and overall space
constraints of the dual-port RAM.
3 I Interrupt.
0 No interrupt is generated after this buffer is filled.
1 SMCE[RXB] is set when the CP completely fills this buffer indicating that the core must process
the buffer. The RXB bit can cause an interrupt if it is enabled.
4–5 — Reserved, should be cleared.
6 CM Continuous mode.
0 Normal operation.
1 The CP does not clear E after this BD is closed, allowing the buffer to be overwritten when the CP
next accesses this BD. However, E is cleared if an error occurs during reception, regardless of
how CM is set.
7–13 — Reserved, should be cleared.
14 OV Overrun. Set when a receiver overrun occurs during reception. The CP writes OV after the received
data is placed into the buffer.
15 — Reserved, should be cleared.
Data length and buffer pointer fields are described in Section 20.2, "SCC Buffer
Descriptors (BDs)."
28.4.9 SMC Transparent TxBD
Data is sent to the CP for transmission on an SMC channel by arranging it in buffers
referenced by the channel TxBD table. The CP uses BDs to confirm transmission or
indicate error conditions so the processor knows buffers have been serviced.
0 1 2
Offset + 0 R — W
Offset + 2
Offset + 4
Offset + 6
MOTOROLA
Freescale Semiconductor, Inc.
3 4 5 6
I L — CM
Tx Data Buffer Pointer
Table 28-14. SMC Transparent TxBD
Chapter 28. Serial Management Controllers (SMCs)
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Description
7 8 9 10
—
Data Length
SMC in Transparent Mode
11 12 13 14 15
UN —
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