Motorola PowerQUICC II MPC8280 Series Reference Manual page 1440

REV_NUM, 14-11
RTSCR, 14-10
RTSR, 14-11
CPM multiplexing logic (CMX)
block diagram, 16-2
overview, 16-1
dual-port RAM
buffer descriptors, 14-22
overview, 14-18
parameter RAM, 14-23
fast communications controllers (FCCs)
Fast Ethernet mode
address recognition, 36-16
block diagram, 36-3
CAM interface, 36-9
collision handling, 36-19
connecting to the MPC8280, 36-5
error handling, 36-20
FCCE, 36-23
FCCM, 36-23
features list, 36-3
FPSMR, 36-21
frame reception, 36-7
frame transmission, 36-6
hash table algorithm, 36-18
hash table effectiveness, 36-19
interpacket gap time, 36-19
interrupt events, 36-25
loopback mode, 36-19
parameter RAM, 36-10
programming model, 36-13
registers, 36-21
RMON support, 36-15
RxBD, 36-25
TxBD, 36-28
HDLC mode
bit stuffing, 37-1
error control, 37-1
error handling, 37-6
FCCE, 37-14
FCCM, 37-14
FCCS, 37-16
features list, 37-2
FPSMR, 37-8
frame reception, 37-3
frame transmission, 37-2
overview, 37-1
parameter RAM, 37-4
programming model, 37-5
receive commands, 37-6
reception errors, 37-7
RxBD, 37-9
transmission errors, 37-7
transmit commands, 37-6
Index-6
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MPC8280 PowerQUICC II Family Reference Manual
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TxBD, 37-12
overview
block diagram, 30-3
disabling FCCs, 30-21
FCCEx, 30-15
FCCMx, 30-15
FCCSx, 30-16
FCRx, 30-14
FDSRx, 30-8
FPSMRx, 30-8
FTODRx, 30-9
GFMRx, 30-3
initialization, 30-16
interrupt handling, 30-17
interrupts, 30-15
overview, 30-2
parameter RAM, 30-12
RxBD, 30-10
saving power, 30-23
switching protocols, 30-23
timing control, 30-18
TxBD, 30-10
transparent mode
achieving synchronization, 38-2
external synchronization signals, 38-3
features list, 38-1
in-line synchronization pattern, 38-3
receive operation, 38-2
synchronization example, 38-4
transmit operation, 38-2
features list, 14-1
2
I C controller
block diagram, 40-1
BRGCLK, 40-2
clocking and pin functions, 40-2
commands, 40-12
features list, 40-2
loopback testing, 40-4
master read (slave write), 40-4
master write (slave read), 40-4
multi-master considerations, 40-5
parameter RAM, 40-9
programming model, 40-6
registers, 40-6
RxBD, 40-13
slave read (master write), 40-4
slave write (master read), 40-4
transfers, 40-3
TxBD, 40-14
IDMA emulation
auto buffer, 19-17
buffer chaining, 19-17
buffers, 19-25
bus exceptions, 19-29
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