Motorola PowerQUICC II MPC8280 Series Reference Manual page 804

SCC BISYNC Receive BD (RxBD)
Table 23-10. PSMR Field Descriptions (continued)
Bits Name
12–13 RPM Receiver parity mode. Selects the type of parity check that the receiver performs. RPM can be
modified on-the-fly and is ignored unless CRC = 11 (LRC). Receive parity errors cannot be disabled
but can be ignored.
00 Odd parity. The transmitter counts ones in the data word. If the sum is not odd, the parity bit is
set to ensure an odd number. An even sum indicates a transmission error.
01 Low parity. If the parity bit is not low, a parity error is reported.
10 Even parity. An even number must result from the calculation performed at both ends of the line.
11 High parity. If the parity bit is not high, a parity error is reported.
14–15 TPM Transmitter parity mode. Selects the type of parity the transmitter performs and can be modified
on-the-fly. TPM is ignored unless CRC = 11 (LRC).
00 Odd parity.
01 Force low parity (always send a zero in the parity bit position).
10 Even parity.
11 Force high parity (always send a one in the parity bit position).
23.12 SCC BISYNC Receive BD (RxBD)
The CP uses BDs to report on each buffer received. It closes the buffer, generates a
maskable interrupt, and starts receiving data into the next buffer after any of the following:
• A user-defined control character is received.
• An error is detected.
• A full receive buffer is detected.
• The
ENTER HUNT MODE
• The
CLOSE RX BD
Figure 23-6 shows the SCC BISYNC RxBD.
0 1 2
Offset + 0 E — W
Offset + 2
Offset + 4
Offset + 6
23-12
Freescale Semiconductor, Inc.
command is issued.
command is issued.
3 4 5 6
I C B CM
Rx Data Buffer Pointer
Figure 23-6. SCC BISYNC RxBD
MPC8280 PowerQUICC II Family Reference Manual
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Description
7 8 9 10
— DE — DL
Data Length
11 12 13 14 15
PR CR OV CD
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