Motorola PowerQUICC II MPC8280 Series Reference Manual page 1163

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Table 32-12. AAL1 CES TxBD Field Descriptions (continued)
Offset
Bits
Name
0x02
DL
0x04
TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. The buffer may
32.13 AAL1 CES Exceptions
There are four circular interrupt queues available for each channel. The interrupt queue
number is programmed in RCT[INTQ] and TCT[INTQ]. Events can be masked by clearing
interrupt mask bits in the RCT and TCT.
When one of the AAL1 channels generates an interrupt request, the CP writes a new entry
to the table consisting of the channel's number and a description of the exception. The valid
(V) bit is then set and INTQ_PTR is incremented. When INTQ_PTR reaches the entry in
which W is set, it returns to the first entry of the queue. Each one-word entry provides
detailed interrupt information to the host. More details can be found in Section 29.11,
"ATM Exceptions."
32.13.1
AAL1 CES Interrupt Queue Entry
The figure below shows an interrupt queue entry.
0
1
2
Offset + 0x00
V
W
Offset + 0x02
Figure 32-30. AAL1 CES Interrupt Queue Entry
The table below describes interrupt queue entry fields.
Table 32-13. AAL1 CES Interrupt Queue Entry Field Descriptions
Offset
Bits
Name
0x00
0
V
1
2
W
3–7
MOTOROLA
Freescale Semiconductor, Inc.
The number of octets the ATM controller should transmit from this BD's buffer. It is not
modified by the CP. The value of DL should be greater than zero.
reside in either internal or external memory. This value is not modified by the CP.
3
7
8
SLIPE
Channel Code (CC)
Valid interrupt entry
0 This interrupt queue entry is free and can be use by the CP.
1 This interrupt queue entry is valid. The host should read this interrupt and clear this
bit.
Wrap bit. When set, this is the last interrupt circular table entry. During initialization, the
host must clear all W bits in the table except the last one, which must be set.
Chapter 32. ATM AAL1 Circuit Emulation Service
For More Information On This Product,
Go to: www.freescale.com
AAL1 CES Exceptions
Description
9
10
11
SLIPS
CASUP
TBNR
Description
12
13
14
15
RXF
BSY
TXB
RXB
32-43

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