Motorola PowerQUICC II MPC8280 Series Reference Manual page 1451

mode registers (DMAMRx), 9-94
next descriptor address registers
(DMANDARx), 9-100
source address registers (DMASARx), 9-98
status registers (DMASRx), 9-96
error handling, 9-103
interrupt and error signals, 9-104
embedded utilities, 9-107
error reporting, 9-104
illegal register access error, 9-105
parity error (PERR), 9-104
PCI bus error signals, 9-104
PCI interface, 9-105, 9-106
system error (SERR), 9-104
in MPC8280, 9-2
initialization, 9-3
interface, 9-6
bus arbitration, 9-21
alogrithm, 9-22
master latency timer, 9-23
parking, 9-21
operation, 9-7
bus commands, 9-7
bus transactions
read and write, 9-10
termination, 9-12
error functions, 9-19
parity, 9-19
reporting, 9-20
other bus operations, 9-15
agent mode configuration access,
9-18
data streaming, 9-15
device selection, 9-15
fast back-to-back transactions, 9-15
host mode configuration access,
9-16
interrupt acknowledge, 9-19
special cycle command, 9-18
protocol fundamentals, 9-8
addressing, 9-9
basic transfer control, 9-8
bus driving and turnaround, 9-10
byte enable signals, 9-10
interrupts from, 9-4
message unit (I2O), 9-70
door bell registers, 9-72
inbound (IDR), 9-73
outbound (ODR), 9-72
I20 unit, 9-74
I20 registers, 9-83
inbound FIFO queue port register
(IFQPR), 9-83
inbound message interrupt mask
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register (IMIMR), 9-87
inbound message interrupt status
register (IMISR), 9-86
messaging unit control register
(MUCR), 9-88
outbound FIFO queue port register
(OFQPR), 9-83
outbound message interrupt mask
register (OMIMR), 9-85
outbound message interrupt status
register (OMISR), 9-84
queue base
(QBAR), 9-89
inbound FIFOs, 9-76
PCI configuration identification, 9-75
inbound FIFOs
Free_FIFO head pointer register (IFHPR), 9-76
Free_FIFO tail pointer register (IFTPR), 9-76
post_FIFO head pointer register (IPHPR), 9-77
post_FIFO tail pointer register (IPTPR), 9-77
message registers, 9-71
inbound message registers (IMRx), 9-71
outbound message registers (OMRx), 9-71
outbound FIFOs, 9-79
free_FIFO head pointer register (OFHPR),
9-79
free_FIFO tail pointer register (OFTPR), 9-79
post_FIFO head pointer register (OPHPR),
9-81
post_FIFO head pointer register (OPTPR), 9-81
PCI parity operation, 9-20
SDMA interface, 9-3
signals, 9-3
single beat read example, 9-11
single beat write example, 9-12
structure, 9-2
target-initiated terminations, 9-13
PDATx (port data) registers, 41-2
PDIRx (port data direction registers), 41-3
PDTEA (SDMA 60x bus transfer error address
register), 19-4
PDTEM (SDMA 60x bus transfer error MSNUM
register), 19-4
PISCR (periodic interrupt status and control register),
4-47
PITC (periodic interrupt timer count register), 4-48
PITR (periodic interrupt timer register), 4-49
PLL pins,, 10-5
PLPRCR,, 10-7
PODRx (port open-drain registers), 41-2
PORESET,, 6-14
Power consumption
FCCs, 30-23
SCCs, 20-27
address register
Index-17