Motorola PowerQUICC II MPC8280 Series Reference Manual page 1360

Features
39.1 Features
The following is a list of the SPI's main features:
• Four-signal interface (SPIMOSI, SPIMISO, SPICLK, and SPISEL) multiplexed
with port D signals
• Full-duplex operation
• Works with data characters from 4 to 16 bits long
• Supports back-to-back character transmission and reception
• Master or slave SPI modes supported
• Multimaster environment support
• Continuous transfer mode for automatic scanning of a peripheral
• Supports maximum clock rates of 25 in master mode and 50 MHz in slave mode,
assuming a 100-MHz system clock
• Independent programmable baud rate generator
• Programmable clock phase and polarity
• Open-drain outputs support multimaster configuration
• Local loopback capability for testing
39.2 SPI Clocking and Signal Functions
The SPI can be configured as a slave or as a master in single- or multiple-master
environments. The master SPI generates the transfer clock SPICLK using the SPI baud rate
generator (BRG). The SPI BRG takes its input from BRGCLK, which is generated in the
MPC8280 clock synthesizer.
SPICLK is a gated clock, active only during data transfers. Four combinations of SPICLK
phase and polarity can be configured with SPMODE[CI, CP]. SPI signals can also be
configured as open-drain to support a multimaster configuration in which a shared SPI
signal is driven by the MPC8280 or an external SPI device.
The SPI master-in slave-out SPIMISO signal acts as an input for master devices and as an
output for slave devices. Conversely, the master-out slave-in SPIMOSI signal is an output
for master devices and an input for slave devices. The dual functionality of these signals
allows the SPIs in a multimaster environment to communicate with one another using a
common hardware configuration.
• When the SPI is a master, SPICLK is the clock output signal that shifts received data
in from SPIMISO and transmitted data out to SPIMOSI. SPI masters must output a
slave select signal to enable SPI slave devices by using a separate general-purpose
I/O signal. Assertion of an SPI's SPISEL while it is master causes an error.
39-2
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MPC8280 PowerQUICC II Family Reference Manual
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