Motorola PowerQUICC II MPC8280 Series Reference Manual page 1398

Port Registers
Table 41-2 describes PDIR fields.
Bits Name
0–31 DRx Direction. Indicates whether a pin is used as an input or an output. Note that bits DR0–DR3 are valid
for PDIRA and PDIRC only.
0 The corresponding pin is an input or is bidirectional.
1 The corresponding pin is an output.
41.2.4 Port Pin Assignment Register (PPAR)
The port pin assignment register (PPAR) is cleared at system reset.
0 1 2
1 1 1
Field DD0 DD1 DD2
Reset
R/W
Addr 0x10D04 (PPARA), 0x10D24 (PPARB), 0x10D44 (PPARC), 0x10D64 (PPARD)
16 17 18
Field DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31
Reset
R/W
Addr 0x10D06 (PPARA), 0x10D26 (PPARB), 0x10D46 (PPARC), 0x10D66 (PPARD)
1
These bits are valid for PPARA and PPARC only
Figure 41-4. Port Pin Assignment Register (PPARA–PPARD)
Table 41-2 describes PPARx fields.
Bits Name
0–31 DDx Dedicated enable. Indicates whether a pin is a general-purpose I/O or a dedicated peripheral pin.
Note: Bits DD0–DD3 are valid for PPARA and PPARC only.
0 General-purpose I/O. The peripheral functions of the pin are not used.
1 Dedicated peripheral function. The pin is used by the internal module. The on-chip peripheral
function to which it is dedicated can be determined by other bits such as those is the PDIR.
41.2.5 Port Special Options Registers A–D (PSORA–PSORD)
Figure 41-5 shows the port special options registers (PSORx).
41-4
Freescale Semiconductor, Inc.
Table 41-2. PDIR Field Descriptions
3 4 5 6
1
DD3 DD4 DD5 DD6
0000_0000_0000_0000
19 20 21 22
0000_0000_0000_0000
Table 41-3. PPAR Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
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Description
7 8 9 10
DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
R/W
23 24 25 26
R/W
Description
11 12 13 14 15
27 28 29 30 31
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