Motorola PowerQUICC II MPC8280 Series Reference Manual page 1119

used, CPM performance is consumed generating the idle cell payload and using the
scheduling algorithm to fill the unused bandwidth at the higher PHY rate.
For example, suppose a system uses a 155.52-Mbps OC-3 device as PHY0, but the
maximum required data rate is only 100 Mbps. In transmit internal rate mode, the user can
configure the internal rate mechanism to clock the ATM transmitter at a cell rate of 100
Mbps. If the system clock is 133 MHz, program a BRG to divide the system clock by 563
to generate a transmit cell request every 563 CPM clocks:
Set FTIRRx_PHY0[TRM] to enable the transmit internal rate mode and clear
FTIRRx_PHY0[Initial Value] since there is no need to further divide the BRG. See
Section 31.15.1.1, "FCC Transmit Internal Rate Register (FTIRRx)."
In external rate mode, however, the transmit cell request frequency is determined by the
PHY's maximum rate, not by internal FCC counters. If an OC-3 PHY is used with the ATM
controller in external rate mode, the requests must be generated every 362 CPM clocks
(assuming a 133-MHz CPM clock). If only 100 Mbps is used for real data, 36% of the
transmit cell requests consume CPM processing time sending idle cells.
31.17.2 APC Configuration
Maximizing the number of cells per slot (CPS) and minimizing the priority levels defined
in the APC data structure improves CPM performance:
• Cells per slot. CPS defines the maximum number of ATM cells allowed to be sent
during a time slot. (See Section 31.3.3.1, "Determining the Cells Per Slot (CPS) in
a Scheduling Table.") The scheduling algorithm is more efficient sending multiple
cells per time slot using the linked-channel field. Therefore, choose the maximum
number of cells per slot allowed by the application.
• Priority levels. The user can configure the APC data structure to have from one to
eight priority levels. (See Section 31.3.6, "Determining the Priority of an ATM
Channel.") For each time slot, the scheduling algorithm scans all priority levels and
maintains pointers for each level. Therefore, enable only the minimum number of
priority levels required.
31.17.3 Buffer Configuration
Using statically allocated buffers of optimal sizes also improves CPM performance:
• Buffer size. Opening and closing buffer descriptors consumes CPM processing time.
Because smaller buffers require more opening and closing of BDs, the optimal
buffer size for maximum CPM performance is equal to the packet size (an AAL5
frame, for example).
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
Freescale Semiconductor, Inc.
Configuring the ATM Controller for Maximum CPM Performance
( × (
133MHz 53
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100Mbps
For More Information On This Product,
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8
= 563
31-105