Motorola PowerQUICC II MPC8280 Series Reference Manual page 1449

transparent mode, 28-7
UART mode, 28-7
Microcode revision number, 14-11
Modes
60x bus mode
60x-compatible bus mode, 8-3
address latch enable (ALE), 11-12
data streaming mode, 8-27
extended transfer mode, 8-20
no-pipeline mode, 8-26
one-level pipeline mode, 8-26
single-MPC8280 bus mode, 8-2
ATM controller
APC modes, 31-10
external rate mode, 31-7
internal rate mode, 31-7
transmit rate modes, 31-7
BISYNC mode, 23-1
cascaded mode, 18-3
echo mode, 28-1
HDLC mode, 22-1
hunt mode, 21-10
IDMA emulation
edge-sensitive mode, 19-16
external request mode, 19-9
level-sensitive mode, 19-16
normal mode, 19-10
loopback mode, 28-1
NMSI mode, synchronization, 24-3
SCC AppleTalk mode, 26-1
serial interface (SI)
echo mode, 15-7
serial peripheral interace (SPI)
master mode, 39-3
slow go, 18-2
transparent mode
overview, 38-1
serial communications controllers (SCCs), 24-1
serial management controllers (SMCs), 28-22
UART mode
serial communications controllers (SCCs), 21-1
serial management controllers (SMCs), 28-11
MPTPR (memory refresh timer prescaler register),
11-33
Multi-channel controllers (MCCs)
CHAMR
HDLC mode, 29-9
transparent mode, 29-13, 29-16
channel extra parameters, 29-29
commands, 29-35
data structure organization, 29-2
exceptions, 29-37
features list, 29-1
global parameters, 29-4, 29-15
MOTOROLA
Freescale Semiconductor, Inc.
Index
For More Information On This Product,
Go to: www.freescale.com
HDLC parameters (channel-specific), 29-6
initialization, 29-49
INTMSK, 29-16
MCCE, 29-38
MCCFx, 29-34
MCCM, 29-38
parameters for transparent operation, 29-11
RSTATE, 29-10
RxBD, 29-45
TSTATE, 29-7
TxBD, 29-47
MxMR (machine x mode registers), 11-27
N
NMSI (non-multiplexed serial interface)
configuration, 16-4
SMC NMSI connection, receive and transmit, 28-2
synchronization in NMSI mode, transparent
operation, 24-3
O
Operations
atomic bus operation, 11-10
digital phase-locked loop (DPLL) operation, 20-22
SMC buffer descriptor, 28-5
transparent operation, NMSI sychronization, 24-3
ORx (option registers), 11-16
P
Parallel I/O ports
block diagram, 41-6
features, 41-1
overview, 41-1
PDATx, 41-2
PDIRx, 41-3
pin assignments (port A–port D), 41-8-41-20
PODRx, 41-2
port C interrupts, 41-20
port pin functions, 41-6
PPAR, 41-4
programming options, 41-8
PSORx, 41-4
registers, 41-2
Parameter RAM
ATM controller, 31-40
fast communications controllers (FCCs)
Fast Ethernet mode, 36-10
HDLC mode, 37-4
overview, 30-12
HDLC mode, 22-3
2
I C controller, 40-9
IDMA emulation, 19-18
Index-15