Motorola PowerQUICC II MPC8280 Series Reference Manual page 1232

Freescale Semiconductor, Inc.
IMA Microcode Architecture
a link is added or removed from the group, software must update the IDCR timer table
entry.
The IDCR timer table entries are maintained by the CPM according to the IDCR master
timer. For each IDCR master timer tick, the IDCR timer table entries are updated. When an
IDCR timer table entry times out, it triggers cell processing for one cell from the delay
compensation buffers of its associated IMA group. The timer table entry is then reset
according to its IDCR request rate.
For this function to operate reliably and regularly, an adequate amount of CPM processing
bandwidth must be reserved for the microcode task that services the IDCR timers. If care
is not taken with this aspect of system design, then the IDCR task might miss the cell
processing of incoming cells, resulting in the eventual overflow of the delay compensation
buffers. In order to ensure against this, it is recommended to either (1) program the IDCR
to run as a high-priority CPM task, or (2) leave an adequate margin of CPM performance,
on the order of 15%.
One additional benefit from IDCR-regulated cell processing is the microcode support for
IMA group service timeouts. If an active IMA group experiences 3 IDCR tick timeouts
without having a data cell available in its delay compensation buffers, then the group is
determined to have stalled and an error interrupt is provided to software.
34.3.3.3 Cell Processing Task
The cell processing task is triggered by the cell processing activation function. When the
cell processing task is triggered, it will extract cells in-order from the delay compensation
buffers. Cells extracted from the delay compensation buffers are processed per the standard
MPC8280 ATM operation (i.e. mapped into ATM channels and processed per the
appropriate AAL or OAM function).
If the on-demand cell processing activation function is used, then when the cell processing
task is triggered, it will extract cells in-order from the delay compensation buffers until
either (1) no more are available, or (2) four cells have been extracted. The purpose of
limiting the cell processing task to a maximum of four cells is to limit the maximum latency
of servicing requests from the external PHYs. Note that, on the average, the receive process
will deliver one cell to the ATM layer per cell reception.
If the IDCR-regulated processing activation function is used, then one cell will be extracted
from the delay compensation buffers of a particular IMA group per timeout of that group's
IDCR timer.
34-22 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA
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