Motorola PowerQUICC II MPC8280 Series Reference Manual page 654

CMX Registers
0 1 2
Field — FC1
Reset
R/W
Addr
16 17 18
Field — FC3
Reset
R/W
Addr
Figure 16-10. CMX FCC Clock Route Register (CMXFCR)
Table 16-5 describes CMXFCR fields.
Bits Name
0 — Reserved, should be cleared
1 FC1 Defines the FCC1 connection
0 FCC1 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus FCCn pins is made in the parallel I/O
control register.
1 FCC1 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes.
2–4 RF1CS Receive FCC1 clock source (NMSI mode). Ignored if FCC1 is connected to the TSA (FC1 = 1).
000 FCC1 receive clock is BRG5.
001 FCC1 receive clock is BRG6.
010 FCC1 receive clock is BRG7.
011 FCC1 receive clock is BRG8.
100 FCC1 receive clock is CLK9.
101 FCC1 receive clock is CLK10.
110 FCC1 receive clock is CLK11.
111 FCC1 receive clock is CLK12.
5–7 TF1CS Transmit FCC1 clock source (NMSI mode). Ignored if FCC1 is connected to the TSA (FC1 = 1).
000 FCC1 transmit clock is BRG5.
001 FCC1 transmit clock is BRG6.
010 FCC1 transmit clock is BRG7.
011 FCC1 transmit clock is BRG8.
100 FCC1 transmit clock is CLK9.
101 FCC1 transmit clock is CLK10.
110 FCC1 transmit clock is CLK11.
111 FCC1 transmit clock is CLK12.
16-14
Freescale Semiconductor, Inc.
4 5
RF1CS TF1CS
0000_0000_0000_0000
20 21
RF3CS TF3CS
0000_0000_0000_0000
Table 16-5. CMXFCR Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
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7 8 9 10
FC2 RF2CS
R/W
0x11B04
23 24
R/W
0x11B06
Description
12 13 15
TF2CS
31
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