Motorola PowerQUICC II MPC8280 Series Reference Manual page 1397

If a port pin is selected as a general-purpose I/O pin, it can be accessed through the port
data register (PDATx). Data written to the PDATx is stored in an output latch. If a port pin
is configured as an output, the output latch data is gated onto the port pin. In this case, when
PDATx is read, the port pin itself is read. If a port pin is configured as an input, data written
to PDATx is still stored in the output latch, but is prevented from reaching the port pin. In
this case, when PDATx is read, the state of the port pin is read.
0 1 2
1 1 1
Field D0 D1 D2
Reset
R/W
Addr 0x10D10 (PDATA), 0x10D30 (PDATB), 0x10D50 (PDATC), 0x10D70 (PDATD)
16 17 18
Field D16 D17 D18
Reset
R/W
Addr 0x10D12 (PDATA), 0x10D32 (PDATB), 0x10D52 (PDATC), 0x10D72 (PDATD)
1
These bits are valid for PDATA and PDATC only
Figure 41-2. Port Data Registers (PDATA–PDATD)
41.2.3 Port Data Direction Registers (PDIRA–PDIRD)
The port data direction register(PDIR), shown in Figure 41-3, is cleared at system reset.
0 1 2
1 1 1
Field DR0 DR1 DR2
Reset
R/W
Addr 0x10D00 (PDIRA), 0x10D20 (PDIRB), 0x10D40 (PDIRC), 0x10D60 (PDIRD)
16 17 18
Field DR16 DR17 DR18 DR19 DR20 DR21 DR22 DR23 DR24 DR25 DR26 DR27 DR28 DR29 DR30 DR31
Reset
R/W
Addr 0x10D02 (PDIRA), 0x10D22 (PDIRB), 0x10D42 (PDIRC), 0x10D62 (PDIRD)
1
These bits are valid for PDIRA and PDIRC only
Figure 41-3. Port Data Direction Register (PDIR)
MOTOROLA
Freescale Semiconductor, Inc.
3 4 5 6
1
D3 D4 D5 D6
19 20 21 22
D19 D20 D21 D22
3 4 5 6
1
DR3 DR4 DR5 DR6
0000_0000_0000_0000
19 20 21 22
0000_0000_0000_0000
Chapter 41. Parallel I/O Ports
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7 8 9 10
D7 D8 D9 D10
—
R/W
23 24 25 26
D23 D24 D25 D26
—
R/W
7 8 9 10
DR7 DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15
R/W
23 24 25 26
R/W
Port Registers
11 12 13 14
D11 D12 D13 D14 D15
27 28 29 30
D27 D28 D29 D30 D31
11 12 13 14
27 28 29 30
41-3
15
31
15
31