Motorola PowerQUICC II MPC8280 Series Reference Manual page 1341

Table 37-1. FCC HDLC-Specific Parameter RAM Memory Map (continued)
1
Offset Name Width
0x5E HMASK Hword HMASK and HADDR[1–4]. The HDLC controller reads the frame address from the
0x60 HADDR1 Hword
0x62 HADDR2 Hword
0x64 HADDR3 Hword
0x66 HADDR4 Hword
0x68 TS_TMP Hword Temporary storage
0x6A TMP_MB Hword Temporary storage
1
Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 14.5.2, "Parameter RAM."
2
DISFC, CRCEC, ABTSC, and NMARC—These 16-bit (modulo 216) counters are maintained by the CP. The user can
initialize them while the channel is disabled.
Figure 37-2 shows an example of using HMASK and HADDR[1–4].
16-Bit Address Recognition
Flag Address Address
0x7E 0x68
HMASK
HADDR1
HADDR2
HADDR3
HADDR4
Recognizes one 16-bit address (HADDR1) and
the 16-bit broadcast address (HADDR2)
Figure 37-2. HDLC Address Recognition Example
37.5 Programming Model
The core configures each FCC to operate in the protocol specified in GFMR[MODE]. The
HDLC controller uses the same data structure as other modes. This data structure supports
multibuffer operation and address comparisons.
37.5.1 HDLC Command Set
The transmit and receive commands are issued to the CPCR; see Section 14.4, "Command
Set."
MOTOROLA
Freescale Semiconductor, Inc.
HDLC receiver, checks it against the four address register values, and masks the
result with HMASK. In HMASK, a 1 represents a bit position for which address
comparison should occur; 0 represents a masked bit position. When addresses
match, the address and subsequent data are written into the buffers. When addresses
do not match and the frame is error-free, the nonmatching address received counter
(NMARC) is incremented.
Note that for 8-bit addresses, mask out (clear) the eight high-order bits in HMASK. The
eight low-order bits and HADDRx should contain the address byte that immediately
follows the opening flag. For example, to recognize a frame that begins 0x7E (flag),
0x68, 0xAA, using 16-bit address recognition, HADDRx should contain 0xAA68 and
HMASK should contain 0xFFFF. See Figure 37-2.
Control
etc.
0xAA 0x44
0xFFFF
0xAA68
0xFFFF
0xAA68
0xAA68
Chapter 37. FCC HDLC Controller
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Programming Model
Description
8-Bit Address Recognition
Flag Address Control
0x7E 0x55
HMASK 0x00FF
0xXX55
HADDR1
0xXX55
HADDR2
0xXX55
HADDR3
0xXX55
HADDR4
Recognizes one 8-bit address (HADDR1)
etc.
0x44
37-5