Motorola PowerQUICC II MPC8280 Series Reference Manual page 1183

Table 33-2. CPS TxQD Field Descriptions (continued)
1
Offset Bits Name
0x0A — Number of
Packets In
Queue
0x0C — NextQueue
0x0E — —
1
Boldfaced entries must be initialized by the user.
33.3.5.3 CPS Buffer Structure
The CPS buffer structure consists of a BD table that points to data buffers. The BDs contain,
apart from the buffer pointer, also the packet header. The buffers contain the packet
payload. See Figure 33-8.
TxBD_Table_Base
Pointers
from
CPS TxQD
TxBD_Table_Offset_Out
TxBD_Table_Base
Pointers
from
another
CPS TxQD
TxBD_Table_Offset_Out
Figure 33-8. Buffer Structure Example for CPS Packets
MOTOROLA
Freescale Semiconductor, Inc.
Counts the number of packets currently in the queue. If this queue is switched, the
receiver increments this counter with each new received packet and the transmitter
decrements it with each packet sent. For switching, the user should initialize this
counter to zero. When this queue is not switched, this counter counts down with every
packet sent. (This can have various purposes such as evaluating the packet rate that
is transmitted from this queue.).
Points to the next TxQD to be serviced after this one. See Section 33.3.2, "Transmit
Priority Mechanism."
Reserved, should be cleared during initialization.
BD memory space
TxBD table
TxBD 1
TxBD 2
TxBD 3
TxBD 4
TxBD 5
TxBD 6
TxBD table
TxBD 1
TxBD 2
TxBD 3
TxBD 4
TxBD 5
TxBD 6
TxBD 7
TxBD 8
TxBD 9
Chapter 33. ATM AAL2
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Go to: www.freescale.com
Description
Data memory space
of ch 1
Tx buffer 1 of
channel 1
Tx buffer 3 of
channel 1
•
Tx buffer 4 of
•
channel 1
•
Tx buffer 1 of
channel 4
of ch 4
Tx buffer 2 of
•
channel 4
•
•
Tx buffer 3 of
channel 4
AAL2 Transmitter
Tx buffer 2 of
channel 1
Tx buffer 8 of
channel 4
33-15