Motorola PowerQUICC II MPC8280 Series Reference Manual page 1441

Table of Contents

Advertisement

commands, 19-28
controlling 60x bus bandwidth, 19-13
DACKx, 19-15
DCM, 19-20
DONEx, 19-16
DREQx, 19-15
DTS/STS programming, 19-23
dual-address transfers, 19-11
edge-sensitive mode, 19-16
exceptions, bus, 19-29
external request mode, 19-9
features list, 19-6
IDMR, 19-25
IDSR, 19-25
level-sensitive mode, 19-16
normal mode, 19-10
operand transfers, recognizing, 19-30
operation, 19-17
overview, 19-5
parallel I/O register programming, 19-30
parameter RAM, 19-18
priorities, 19-14
programming examples, 19-31
programming the parallel I/O registers, 19-30
signals, 19-14
single address transfers (fly-by), 19-12
transfers, 19-6
interrupt controller
memory map, 3-7
multi-channel controllers (MCCs)
CHAMR
HDLC mode, 29-9
transparent mode, 29-13, 29-16
channel extra parameters, 29-29
commands, 29-35
data structure organization, 29-2
exceptions, 29-37
features list, 29-1
global parameters, 29-4, 29-15
HDLC parameters (channel-specific), 29-6
initialization, 29-49
INTMSK, 29-16
MCCE, 29-38
MCCFx, 29-34
MCCM, 29-38
parameters for transparent operation, 29-11
RSTATE, 29-10
RxBD, 29-45
TSTATE, 29-7
TxBD, 29-47
overview, CPM, 14-1
parallel I/O ports
block diagram, 41-6
features, 41-1
MOTOROLA
Freescale Semiconductor, Inc.
Index
For More Information On This Product,
Go to: www.freescale.com
overview, 41-1
PDATx, 41-2
PDIRx, 41-3
pin assignments (port A–port D), 41-8-41-20
PODRx, 41-2
port C interrupts, 41-20
port pin functions, 41-6
PPAR, 41-4
programming options, 41-8
PSORx, 41-4
registers, 41-2
resetting registers and parameters for all channels,
14-13
RISC timer tables
CP loading tracking, 14-30
features list, 14-25
initializing RISC timer tables, 14-28
interrupt handling, 14-29
overview, 14-25
parameter RAM, 14-25
RAM usage, 14-26
RTMR, 14-27
scan algorithm, 14-29
SET TIMER command, 14-28
table entries, 14-27
timer counts, comparing, 14-30
TM_CMD, 14-27
tracking CP loading, 14-30
SDMA channels
bus arbitration, 19-2
bus transfers, 19-2
LDTEA, 19-4
LDTEM, 19-4
overview, 19-1
PDTEA, 19-4
PDTEM, 19-4
programming model, 19-3
registers, 19-3
SDMR, 19-4
SDSR, 19-3
serial configuration, 14-3
serial peripheral interface (SPI)
block diagram, 39-1
clocking and pin functions, 39-2
commands, 39-14
configuring the SPI, 39-3
features list, 39-2
interrupt handling, 39-20
master mode, 39-3
maximum receive buffer length (MRBLR), 39-12
multi-master operation, 39-5
parameter RAM, 39-12
programming example
master, 39-18
Index-7

Advertisement

Table of Contents
loading

This manual is also suitable for:

Powerquicc ii mpc8270Powerquicc ii mpc8275Powerquicc ii mpc8280

Table of Contents