Motorola PowerQUICC II MPC8280 Series Reference Manual page 1042

Available Bit Rate (ABR) Flow Control
31.5.2 RM Cell Structure
Table 31-7 describes the structure of the RM cell supported by the MPC8280. For more
information, see the ABR flow-control traffic management specification (TM 4.0) on the
ATM Forum website.
Table 31-7. Fields and their Positions in RM Cells
Fields Octet Bits
Header 1–5 All
ID 6 All
DIR 7 0
BN 7 1
CI 7 2
NI 7 3
RA 7 4
— 7 5-7
ER 8–9 All
CCR 10–11 All
MCR 12–13 All
QL 14–17 All
SN 18–21 All
— 22–51 All
— 52 0–5 Reserved, should be cleared.
CRC-10 52 6–7 CRC-10
53 All
31.5.2.1 RM Cell Rate Representation
Rates in the RM cells are represented in a binary floating-point format using a 5-bit
exponent (e), a 9-bit mantissa (m), and a 1-bit nonzero flag (nz), as shown in Figure 31-15.
0 1 2
0 nz
31-28
Freescale Semiconductor, Inc.
Description
ATM cell header
Protocol ID
Direction of RM cell (0 = forward, 1 = backward)
Backward notification (BN = 0, the cell was generated by the source;
BN=1, the cell was generated by the network or by the destination)
Congestion indication. (1 = congestion, 0 = otherwise)
No increase indication. (1 = no increase allowed, 0 = otherwise)
Not used (ATM Forum ABR)
Reserved, should be cleared.
Explicit rate; see Section 31.5.2.1
Current cell rate; see Section 31.5.2.1
Minimum cell rate; see Section 31.5.2.1
Not used (ATM Forum ABR)
Not used (ATM Forum ABR)
Reserved, should be cleared.
6 7
Exponent
Figure 31-15. Rate Format for RM Cells
MPC8280 PowerQUICC II Family Reference Manual
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Value
RM-VCC
PTI=6
1
0
0
0
0
0x6A for each byte
0
Mantissa
MOTOROLA
15