Motorola PowerQUICC II MPC8280 Series Reference Manual page 1115

0 1 2
Field TIRU TIRU TIRU
0 1 2
Reset
R/W
Addr
16 17 18
Field TIRU TIRU TIRU
16 17 18
Reset
R/W
Addr
Figure 31-65. FCC Internal Rate Event Register (FIRERx)
Table 31-52 describes FIRERx fields.
Table 31-52. FIRERx Field Descriptions (TIREM=1)
Bit Name
0–30 TIRUy Transmit internal rate underrun
0 There is no transmission underrun for this PHY.
1 Transmit internal rate underrun or PHY address y has occurred. Bit is cleared by writing 1 to it.
Writing 0 has no effect on value.
31 — Reserved, should be cleared.
31.15.1.6 FCC Internal Rate Selection Registers (FIRSRx_HI,
FIRSRx_LO)
If TIREM = 1, each PHY can be assigned one of four rates, as configured by the four FCC
transmit internal rate timers. The FCC internal rate selection registers (FIRSRx_HI,
FIRSRx_LO), shown in Figure 31-66 and Figure 31-67, assign rate group to each of the
PHYs.
MOTOROLA Chapter 31. ATM Controller and AAL0, AAL1, and AAL5
Freescale Semiconductor, Inc.
Transmission Rate Modes—External, Internal, and Expanded Internal
3 4 5 6
TIRU TIRU TIRU TIRU TIRU
3 4 5 6
0000_0000_0000_0000
0x11384 (FIRER1), 0x113A4 (FIRER2)
19 20 21 22
TIRU TIRU TIRU TIRU TIRU
19 20 21 22
0000_0000_0000_0000
0x11386 (FIRER1), 0x113A6 (FIRER2)
For More Information On This Product,
Go to: www.freescale.com
7 8 9 10 11
TIRU TIRU TIRU TIRU
7 8 9 10 11
R/W
23 24 25 26 27
TIRU TIRU TIRU TIRU
23 24 25 26 27
R/W
Description
12 13 14 15
TIRU TIRU TIRU TIRU
12 13 14 15
28 29 30 31
TIRU TIRU TIRU —
28 29 30
31-101