Motorola PowerQUICC II MPC8280 Series Reference Manual page 1457

receive buffer, 25-17
transmit buffer, 25-19
HDLC mode
accessing the bus, 22-21
bus controller, 22-18
collision detection, 22-18, 22-22
commands, 22-5
delayed RTS mode, 22-23
error handling, 22-6
features list, 22-2
GSMR, HDLC bus protocol programming, 22-25
interrupts, 22-15
memory map, 22-4
multi-master bus configuration, 22-20
overview, 22-1
parameter RAM, 22-3
performance, increasing, 22-22
programming example, 22-16, 22-25
programming the controller, 22-5
PSMR, 22-7
RxBD, 22-9
single-master bus configuration, 22-21
TxBD, 22-12
using the TSA, 22-24
overview
buffer descriptors, 20-11
controlling SCC timing, 20-18
DPLL operation, 20-22
features, 20-2
initialization, 20-17
interrupt handling, 20-16
parameter RAM, 20-13
reconfiguration, 20-26
reset sequence, 20-26
switching protocols, 20-27
transparent mode
achieving synchronization, 24-3
commands, 24-7
DSR receiver SYNC pattern lengths, 24-3
end of frame detection, 24-6
error handling, 24-8
frame reception, 24-3
frame transmission, 24-2
inherent synchronization, 24-6
in-line synchronization, 24-6
overview, 24-1
programming example, 24-14
RxBD, 24-9
synchronization signals, 24-4
synchronization, user-controlled, 24-5
transmit synchronization, 24-3
TxBD, 24-11
UART mode
commands, 21-6
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control character insertion, 21-10
data handling, character and message-based, 21-5
error reporting, 21-6
features list, 21-2
fractional stop bits, 21-11
handling errors, 21-12
hunt mode, 21-10
normal asynchronous mode, 21-3
overview, 21-1
parameter RAM, 21-4
programming example, 21-23
RxBD, 21-16
S-records loader application, 21-24
status reporting, 21-6
synchronous mode, 21-3
TxBD, 21-19
Serial configuration, 14-3
Serial interface (SI)
enabling connections, 15-7
features, 15-3
GCI support, 15-32
IDL bus implementation
programming the IDL, 15-30
IDL interface support, 15-26
overview, 15-4
programming GCI, 15-34
programming RAM entries, 15-10
registers, 15-18
see also CPM multiplexing logic (CMX)
SI RAM, 15-8
Serial management controllers (SMCs)
buffer descriptors, overview, 28-5
disabling SMCs on-the-fly, 28-9
disabling the receiver, 28-10
disabling the transmitter, 28-10
enabling the receiver, 28-10
enabling the transmitter, 28-10
features list, 28-2
GCI mode
C/I channel
handling the SMC, 28-34
reception process, 28-34
RxBD, 28-36
transmission process, 28-34
TxBD, 28-37
commands, 28-35
monitor channel
reception process, 28-34
RxBD, 28-35
transmission process, 28-34
TxBD, 28-36
overview, 28-32
parameter RAM, 28-33
memory structure, 28-6
Index-23