Motorola PowerQUICC II MPC8280 Series Reference Manual page 1382

2
I C Controller Transfers
40.3.1 I C Master Write (Slave Read)
2
If the MPC8280 is the master, prepare the transmit buffers and BDs before initiating a write.
Initialize the first transmit data byte with the slave address and write request (R/W = 0).
If the MPC8280 is the slave target of the write, prepare receive buffers and BDs to await
the master's request. Figure 40-4 shows the timing for a master write.
SDA
Note: Data and ACK are repeated n times.
A master write occurs as follows:
1. The master core sets I2COM[STR]. The transfer starts when the SDMA channel
loads the Tx FIFO with data and the I
2. The I 2 C master generates a start condition—a high-to-low transition on SDA while
SCL is high—and the transfer clock SCL pulses for each bit shifted out on SDA. If
the master transmitter detects a multiple-master collision (by sensing a '0' on SDA
while sending a '1'), transmission stops and the channel reverts to slave mode. A
maskable interrupt is sent to the master's core so software can try to retransmit
later.
3. The slave acknowledges each byte and writes to its current receive buffer until a
new start or stop condition is detected.
4. After sending each byte, the master monitors the acknowledge indication. If the
slave receiver fails to acknowledge a byte, transmission stops and the master
generates a stop condition—a low-to-high transition on SDA while SCL is high.
40.3.2 I C Loopback Testing
2
When in master mode, an I
requests. The master I
(programmed in I2ADD). The master's receiver monitors the transmission and reads the
transmitted data into its receive buffer. Loopback operation requires no special register
programming.
40.3.3 I C Master Read (Slave Write)
2
Before initiating a master read with the MPC8280, prepare a transmit buffer of size n+1
bytes, where n is the number of bytes to be read from the slave. The first transmit byte
should be initialized to the slave address with R/W = 1. The next n transmit bytes are used
40-4
Freescale Semiconductor, Inc.
S
T
A
R
T
W
Device Address
2
Figure 40-4. I C Master Write Timing
2
C controller supports loopback operation for master write
2 C controller simply issues a write request directed to its own address
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S
T
O
A A
P
C C
K K
Data Byte
2 C bus is not busy.
MOTOROLA