Motorola PowerQUICC II MPC8280 Series Reference Manual page 976

MCC Exceptions
After an MCC interrupt reaches the core, the software should read the corresponding
MCCE. After clearing the appropriate event bits by writing ones to them, the software may
begin processing the table(s) that contain pending events, as indicated by the bits
MCCE[RINTx] and MCCE[TINT]. When processing the interrupt tables, the software
must clear each entry's valid bit (V) (see Section 29.8.1.1, "Interrupt Circular Table
Entry"). The user follows this procedure until it reaches an entry with V = 0. It may not be
appropriate for an application to process every new entry of all interrupt tables at once,
depending on desired interrupt handler latency or other factors. It is up to the user to
determine an interrupt handling scheme that provides desired performance and
functionality.
29.8.1 MCC Event Register (MCCE)/Mask Register (MCCM)
The MCC event register (MCCE) is used to report events and generate interrupt requests.
For each of its flags, a programmable mask/enable bit in MCCM determines whether an
interrupt request is generated. The MCC mask register (MCCM) is used to enable/disable
interrupt requests. For each flag in the MCCE there is a programmable mask/enable bit in
MCCM which determines whether an interrupt request is generated. Setting an MCCM bit
enables and clearing an MCCM bit disables the corresponding interrupt.
MCCE bits are cleared by writing ones to them; writing zeros has no effect.
Figure 29-19 shows MCCE and MCCM bits.
0 1 2
Field QOV0 RINT0 QOV1 RINT1 QOV2 RINT2 QOV3 RINT3
Reset
R/W
Addr 0x11B30 (MCCE1), 0x11B50 (MCCE2)/0x11B34 (MCCM1), 0x11B54 (MCCM2)
Figure 29-19. MCC Event Register (MCCE)/Mask Register (MCCM)
29-38
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3 4 5
0000_0000_0000_0000
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6 7 8 11
—
R/W
12 13 14 15
TQOV TINT GUN GOV
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