Motorola PowerQUICC II MPC8280 Series Reference Manual page 1314

Freescale Semiconductor, Inc.
Flow Control
When the receiver detects the first bytes of a frame, the Ethernet controller performs
address recognition functions on the frame; see Section 36.12, "Ethernet Address
Recognition." The receiver can receive physical (individual), group (multicast), and
broadcast addresses. Because Ethernet receive frame data is not written to memory until the
internal address recognition algorithm is complete, bus usage is not wasted on frames not
addressed to this station. The receiver can also operate with an external CAM, in which case
frame reception continues normally, unless the CAM specifically signals the frame to be
rejected. See Section 36.7, "CAM Interface."
If an address is recognized, the Ethernet controller fetches the next RxBD and, if it is empty,
starts transferring the incoming frame to the RxBD's associated data buffer.
In half-duplex mode, if a collision is detected during the frame, the RxBDs associated with
this frame are reused. Thus, no collision frames are presented to the user except late
collisions, which indicate serious LAN problems. When the buffer has been filled, the
Ethernet controller clears RxBD[E] and generates an interrupt if RxBD[I] is set. If the
incoming frame is larger than the buffer, the Ethernet controller fetches the next RxBD in
the table; if it is empty, it continues receiving the rest of the frame.
The RxBD length is determined by MRBLR in the parameter RAM. The user should
program MRBLR to be at least 64 bytes. During reception, the Ethernet controller checks
for frames that are too short or too long. When the frame ends, the receive CRC field is
checked and written to the data buffer. The data length written to the last BD in the Ethernet
frame is the length of the entire frame, which enables the software to recognize a
frame-too-long condition.
If an external CAM is used (FPSMRx[CAM] = 1), the Ethernet controller adds the two
lower bytes of the CAM output at the end of each frame. Note that the data length does not
include these two bytes; that is, the extra two bytes could push the buffer length past
MRBLR.
When the receive frame is complete, the Ethernet controller sets RxBD[L], writes the other
frame status bits into the RxBD, and clears RxBD[E]. The Ethernet controller next
generates a maskable interrupt, indicating that a frame was received and is in memory. The
Ethernet controller then waits for a new frame. The Ethernet controller receives serial data
least-significant nibble first.
36.6 Flow Control
Because collisions cannot occur in full-duplex mode, Fast Ethernet can operate at the
maximum rate. When the rate becomes too fast for a station's receiver, the station's
transmitter can send flow-control frames to reduce the rate. Flow-control instructions are
transferred by special frames of minimum frame size. The length/type fields of these frames
have a special value. Table 36-1 shows the flow-control frame structure.
36-8 MPC8280 PowerQUICC II Family Reference Manual MOTOROLA
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