Motorola PowerQUICC II MPC8280 Series Reference Manual page 1366

Programming the SPI Registers
Table 39-1. SPMODE Field Descriptions (continued)
Bits Name
7 EN Enable SPI. Do not change other SPMODE bits when EN is set.
0 The SPI is disabled. The SPI is in a reset state and consumes minimal power. The SPI BRG is not
functioning and the input clock is disabled.
1 The SPI is enabled. Configure SPIMOSI, SPIMISO, SPICLK, and SPISEL to connect to the SPI as
described in Section 41.2, "Port Registers. "
8–11 LEN Character length in bits per character. If the character length is not greater than a byte, every byte in
memory holds (LEN+1) valid bits. If the character length is greater than a byte, every half-word holds
(LEN+1) valid bits. See Section 39.4.1.1, "SPI Examples with Different SPMODE[LEN] Values."
0000–0010 Reserved, causes erratic behavior.
0011 4-bit characters
...
1111 16-bit characters
12–15 PM Prescale modulus select. Specifies the divide ratio of the prescale divider in the SPI clock generator.
BRGCLK is divided by 4 * ([PM0–PM3] + 1), a range from 4 to 64. The clock has a 50% duty cycle.
SPICLK (CI = 0)
SPICLK (CI = 1)
SPIMOSI
(From Master)
SPIMISO
(From Slave)
SPISEL
NOTE: Q = Undefined Signal.
Figure 39-5. SPI Transfer Format with SPMODE[CP] = 0
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Description
lsb
lsb Q
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