Motorola PowerQUICC II MPC8280 Series Reference Manual page 1439

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RCCR, 14-9
REV_NUM, 14-11
RTSCR, 14-10
RTSR, 14-11
Communications processor module (CPM)
ATM controller
AAL1 sequence number protection table, 31-83
AALn RxBD, 31-7, 31-74
AALn TxBD, 31-5, 31-79
ABR flow control, 31-9, 31-21
address compression, 31-16
ATM layer statistics, 31-36
ATM memory structure, 31-40
ATM pace control (APC) unit
ATM service types, 31-10
configuration, 31-105
data structure, 31-66
modes, 31-10
overview, 31-9
parameter tables, 31-67
priority table, 31-68
scheduling mechanism, 31-10
scheduling tables, 31-68
traffic type, 31-12
UBR+ traffic, 31-14
VBR traffic, 31-13
command, 31-95
ATM TRANSMIT
ATM-to-ATM data forwarding, 31-39
ATM-to-TDM interworking, 31-36
buffer descriptors, 31-69
exceptions, 31-85
external rate mode, 31-7
FCCE, 31-94
FCCM, 31-94
features list, 31-2
FPSMR, 31-91
GFMR register, 31-91
global mode entry (GMODE), 31-43
internal rate mode, 31-7
interrupt queues, 31-85
maximum performance configuration, 31-104
OAM performance monitoring, 31-31, 31-65
OAM support, 31-29
operations and maintenance (OAM) support,
31-29
overview, 31-5
parameter RAM, 31-40
performance monitoring, 31-9
performance, maximum (configuration), 31-104
programming model, 31-91
receive connection table (RCT)
ATM channel code, 31-45
overview, 31-44
raw cell queue, 31-20
MOTOROLA
Freescale Semiconductor, Inc.
Index
For More Information On This Product,
Go to: www.freescale.com
RCT entry format, 31-47
registers, 31-91
RxBD, 31-74
RxBD extension, 31-79
SRTS generation using external logic, 31-103
transmit connection table (TCT)
AALn protocol-specific TCTs, ??-31-60
ATM channel code, 31-45
overview, 31-44
TCT entry format, 31-54
transmit connection table extension (TCTE)
ABR protocol-specific, 31-62
ATM channel code, 31-45
overview, 31-44
UBR+ protocol-specific, 31-62
VBR protocol-specific, 31-61
transmit rate modes, 31-7
TxBD, 31-79
TxBD extension, 31-83
UDC extended address mode, 31-35
UEAD_OFFSET determination, 31-42
UNI statistics table, 31-84
user-defined cells (UDC)
extended address mode, 31-35
overview, 31-35
RxBD extension (AAL5/AAL1), 31-79
TxBD extension (AAL5/AAL1), 31-83
user-defined RxBD extension (AAL5/AAL1),
31-79
user-defined TxBD extension (AAL5/AAL1),
31-83
UTOPIA interface, 31-87
VCI filtering, 31-43
VCI/VPI address lookup, 31-15
VC-level address compression tables (VCLT),
31-19
VP-level address compression table (VPLT),
31-18
block diagram, 14-3
command set
command descriptions, 14-16
command execution latency, 14-17
command register example, 14-17
CPCR, 14-12
opcodes, 14-15
overview, 14-12
communications processor (CP)
block diagram, 14-6
execution from RAM, 14-8
features list, 14-4
microcode execution from RAM, 14-8
microcode revision number, 14-11
peripheral interface, 14-7
RCCR, 14-9
Index-5

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