Motorola PowerQUICC II MPC8280 Series Reference Manual page 1002

Table of Contents

Advertisement

FCC Parameter RAM
When the CP sees the W bit set in a BD, it returns to the beginning of the BD table after
processing of the BD is complete. After using a BD, the CP clears the E bit (not empty) and
does not use a BD again until the BD has been processed by the core. However, in
continuous mode, available to some protocols, the E bit remains set (always empty).
30.7 FCC Parameter RAM
Each FCC parameter RAM area begins at the same offset from each FCC base area. The
protocol-specific portions of the FCC parameter RAM are discussed in the specific protocol
descriptions. Table 30-5. shows portions common to all FCC protocols.
Some parameter RAM values must be initialized before the FCC is enabled; other values
are initialized/written by the CP. Once initialized, most parameter RAM values do not need
to be accessed by user software because most activity centers around the TxBDs and
RxBDs rather than the parameter RAM. However, if the parameter RAM is accessed, note
the following:
• Parameter RAM can be read at any time.
• Tx parameter RAM can be written only when the transmitter is disabled—after a
STOP TRANSMIT
buffer/frame finishes transmitting after a
before a
RESTART TRANSMIT
• Rx parameter RAM can be written only when the receiver is disabled. Note the
command does not stop reception, but it does allow the user to extract
CLOSE RXBD
data from a partially full Rx buffer.
• See Section 30.12, "Disabling the FCCs On-the-Fly."
Some parameters in Table 30-5. are not described and are listed only to provide information
for experienced users and for debugging. The user need not access these parameters in
normal operation.
Table 30-5. FCC Parameter RAM Common to All Protocols except ATM
1
Offset
Name
Width
0x00
RIPTR
Hword Receive internal temporary data pointer. Used by microcode as a temporary buffer for
0x02
TIPTR
Hword Transmit internal temporary data pointer. Used by microcode as a temporary buffer for
0x04
Hword Reserved, should be cleared.
30-12
Freescale Semiconductor, Inc.
command and before a
command.
data. Must be 32-byte aligned and the size of the internal buffer must be 32 bytes unless
it is stated otherwise in the protocol specification.
data. Must be 32-byte aligned and the size of the internal buffer must be 32 bytes unless
it is stated otherwise in the protocol specification. .
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
command or after the
RESTART TRANSMIT
GRACEFUL STOP TRANSMIT
Description
command and
MOTOROLA

Advertisement

Table of Contents
loading

This manual is also suitable for:

Powerquicc ii mpc8270Powerquicc ii mpc8275Powerquicc ii mpc8280

Table of Contents