Motorola PowerQUICC II MPC8280 Series Reference Manual page 1430

Physical memory. The actual memory that can be accessed through the
Pipelining. Technique that breaks operations, such as instruction processing
Precise exceptions. A category of exception for which the pipeline can be
Primary opcode. The most-significant 6 bits (bits 0–5) of the instruction
Protection boundary. Boundary between protection domains.
Protection domain. A protection domain is a segment, a virtual page, a BAT
Q
Quad word. A group of 16 contiguous locations starting at an address
R
rA. Instruction field that specifies a GPR to be used as a source or
rB. Instruction field that specifies a GPR to be used as a source.
rD. Instruction field that specifies a GPR to be used as a destination.
rS. Instruction field that specifies a GPR to be used as a source.
Real address mode. An MMU mode when no address translation is
Glossary-8
Freescale Semiconductor, Inc.
PowerPC architecture, a page fault exception condition occurs when
a matching, valid page table entry (PTE[V] = 1) cannot be located.
system's memory bus.
or bus transactions, into smaller distinct stages or tenures
(respectively) so that a subsequent operation can begin before the
previous one has completed.
stopped so instructions that preceded the faulting instruction can
complete and subsequent instructions can be flushed and
redispatched after exception handling has completed. See Imprecise
exceptions.
encoding that identifies the type of instruction. See Secondary
opcode.
area, or a range of unmapped effective addresses. It is defined only
when the appropriate relocate bit in the MSR (IR or DR) is 1.
divisible by 16.
destination.
performed and the effective address specified is the same as the
physical address. The processor's MMU is operating in real address
mode if its ability to perform address translation was disabled
through the MSR registers IR or DR bits.
MPC8280 PowerQUICC II Family Reference Manual
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