Motorola PowerQUICC II MPC8280 Series Reference Manual page 867

Peripheral bus
Tx data FIFO
EP0
Rx FIFO
16-byte
USB host
state machine
Receiver
DPLL/
Bus Interface
External transceiver
27.5.1 USB Host Controller Transmit/Receive
The USB host controller initiates all USB transactions in the system. After the reset
condition, the HOST bit in USB mode register should be set (refer to Section 27.5.7.1,
"USB Mode Register (USMOD)") to enable host operation. USEP1 should be programmed
for host operation as described in Section 27.5.7.3, "USB Endpoint Registers
(USEP1–USEP4)."
Once enabled by setting the USMOD[EN] bit, the USB host controller waits for a packet
in its transmit FIFO. When the FIFO contains data for transmission, the host transaction
begins. Figure 27-3 and Table 27-2 describe the behavior of the USB host controller for
each transaction. Low speed transactions start with a preamble that is generated by the USB
host controller state machine when the LSP bit in the TxBD is set.
When USMOD[TEST] is programmed, both the host state machine and function state
machine are active. End points 2-4 receive/transmit data according to tokens received from
MOTOROLA
Freescale Semiconductor, Inc.
Tx data FIFO
16-byte
USB function
state machine
Transmitter
Figure 27-4. USB Controller Block Diagram
Chapter 27. Universal Serial Bus Controller
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Go to: www.freescale.com
USB Host Description
U-bus
Port control
Mode register Command register
Port configuration
mode register
mode register
Endpoint
registers
Address
register
27-9