Motorola PowerQUICC II MPC8280 Series Reference Manual page 521

Freescale Semiconductor, Inc.
User-Programmable Machines (UPMs)
11.6.4.5 The Wait Mechanism
The WAEN bit in the RAM array word, shown in Table 11-36., can be used to enable the
UPM wait mechanism in selected UPM RAM words. Note that the WAEN bit needs to be
set in two consecutive UPM words to get the desired operation.
If the UPM reads a RAM word with the WAEN bit set, the external UPMWAIT signal is
sampled by the memory controller in the following cycle and the request is frozen. The
UPMWAIT signal is sampled at the rising edge of CLKIN. If UPMWAIT is asserted and
WAEN = 1 in the previous UPM word, the UPM is frozen until UPMWAIT is negated. The
value of the external pins driven by the UPM remains as indicated in the previous word read
by the UPM. When UPMWAIT is negated, the UPM continues its normal functions. Note
that during the wait cycles, the UPM negates PSDVAL.
Figure 11-66 shows how the WAEN bit in the word read by the UPM and the UPMWAIT
signal are used to hold the UPM in a particular state until UPMWAIT is negated. As the
example in Figure 11-66 shows, the CSx and GPL1 states (C12 and F) and the WAEN value
(C) are frozen until UPMWAIT is recognized as deasserted. WAEN is typically set before
the line that contain UTA = 1.
MOTOROLA Chapter 11. Memory Controller 11-83
For More Information On This Product,
Go to: www.freescale.com