Motorola PowerQUICC II MPC8280 Series Reference Manual page 1312

Ethernet Channel Frame Transmission
36.3.1 Connecting the MPC8280 to Ethernet (RMII)
Figure 36-4 shows the basic components of the reduced media-independent interface
(RMII) and the signals required for the fast Ethernet connection between the MPC8280 and
a PHY. The MDC/MDIO management interface is the same as in MII. The RMII reference
clock (REF_CLK) is distributed over the FCC transmit clock. In RMII mode receive clock
is not used.
MPC8280
1
The management signals (MDC and MDIO) can be common to all of the fast Ethernet connections in the sys-
tem, assuming that each PHY has a different management address. Use parallel I/O port pins to implement MDC
2
and MDIO. (The I C controller cannot be used for this function.)
Figure 36-4. Connecting the
36.4 Ethernet Channel Frame Transmission
The Ethernet transmitter requires almost no core intervention. When the core enables the
transmitter, the Ethernet controller polls the first TxBD in the FCC's TxBD table every 256
serial clocks. If the user has a frame ready to transmit, setting FTODR[TOD] eliminates
waiting for the next poll. When there is a frame to transmit, the Ethernet controller begins
fetching the data from the data buffer and asserts TX_EN. The preamble sequence, start
frame delimiter, and frame information are sent in that order; see Figure 36-1. In
full-duplex mode, because collisions are ignored, frame transmission maintains only the
interframe gap 28 serial clocks (112 bit time period) regardless of CRS assertion.
There is one internal buffer for out-of-sequence flow control frames (in full-duplex Fast
Ethernet). When the Fast Ethernet controller is between frames, this buffer is polled if flow
control is enabled. This buffer must contain the whole frame.
However, in half-duplex mode, the controller defers transmission if the line is busy (CRS
asserted). Before transmitting, the controller waits for carrier sense to become inactive, at
which point the controller determines if CRS remains negated for 16 serial clocks. If so, the
transmission begins after an additional 8 serial clocks (96 bit-times after CRS originally
36-6
Freescale Semiconductor, Inc.
Clock from board
Reference Clock (REF_CLK)
Transmit di-bit Data (TXD[1:0])
Transmit Enable (TX_EN)
Receive di-bit Data (RXD[1:0])
Receive Error (RX_ER)
Receive CRS_DV (CRS_DV)
Management Data Clock
Management Data I/O
MPC8280 PowerQUICC II Family Reference Manual
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Fast Ethernet
RMII PHY
1
(MDC)
1
(MDIO)
to Ethernet (RMII)
MPC8280
Medium
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