Motorola PowerQUICC II MPC8280 Series Reference Manual page 774

HDLC Mode Register (PSMR)
Table 22-6 describes PSMR HDLC fields.
Bits Name
0-3 NOF Number of flags. Minimum number of flags between or before frames. If NOF = 0b0000, no flags are
inserted between frames and the closing flag of one frame is followed by the opening flag of the next
frame in the case of back-to-back frames. NOF can be modified on-the-fly.
4–5 CRC CRC selection.
00 16-bit CCITT-CRC (HDLC). X16 + X12 + X5 + 1.
x1 Reserved.
10 32-bit CCITT-CRC (Ethernet and HDLC). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +
X8 + X7 + X5 + X4 + X2 + X1 +1.
6 RTE Retransmit enable.
0 No retransmission.
1 Automatic frame retransmission is enabled. Particularly useful in the HDLC bus protocol and
ISDN applications where multiple HDLC controllers can collide. Note that retransmission occurs
only if a lost CTS occurs on the first or second buffer of the frame.
7 — Reserved, should be cleared.
8 FSE Flag sharing enable. FSE can be set only if GSMR_H[RTSM] is already set. Can be modified
on-the-fly.
0 Normal operation.
1 If NOF[0–3] = 0b0000, a single shared flag is sent between back-to-back frames. Other values of
NOF[0–3] are decremented by 1. Useful in signaling system #7 applications.
9 DRT Disable receiver while transmitting.
0 Normal operation.
1 As the SCC sends data, the receiver is disabled and gated by the internal RTS. This helps if the
HDLC channel is on a multidrop line and the SCC does not need to receive its own transmission.
Note: If DRT = 1, GSMR_H[CDS] should be cleared unless both of the following are true: the same
clock is used for TCLK and RCLK, and CTS either has synchronous timing or is always asserted.
10 BUS HDLC bus mode.
0 Normal HDLC operation.
1 HDLC bus operation is selected. See Section 22.14, "HDLC Bus Mode with Collision Detection."
11 BRM HDLC bus RTS mode. Valid only if BUS = 1. Otherwise, it is ignored.
0 Normal RTS operation during HDLC bus mode. RTS is asserted on the first bit of the Tx frame
and negated after the first collision bit is received.
1 Special RTS operation during HDLC bus mode. RTS is delayed by one bit with respect to the
normal case, which helps when the HDLC bus protocol is being run locally and sent over a
long-distance line at the same time. The one-bit delay allows RTS to be used to enable the
transmission line buffers so that the electrical effects of collisions are not sent over the
transmission line.
12 MFF Multiple frames in Tx FIFO. The receiver is not affected.
0 Normal operation. The Tx FIFO must never contain more than one HDLC frame. The CTS lost
status is reported accurately on a per-frame basis.
1 The Tx FIFO can hold multiple frames, but lost CTS may not be reported on the buffer/frame it
occurred on. This can improve performance of HDLC transmissions of small back-to-back frames
or when the number of flags between frames should be limited.
13–15 — Reserved, should be cleared.
22-8
Freescale Semiconductor, Inc.
Table 22-6. PSMR HDLC Field Descriptions
MPC8280 PowerQUICC II Family Reference Manual
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