Motorola PowerQUICC II MPC8280 Series Reference Manual page 720

Features
Table 20-2. GSMR_L Field Descriptions (continued)
Bit Name
14–15 TDCR Transmitter/receiver DPLL clock rate. If the DPLL is not used, choose 1× mode except in
asynchronous UART mode where 8×, 16×, or 32× must be chosen. TDCR should match RDCR in
16–17 RDCR
most applications to allow the transmitter and receiver to use the same clock source. If an
application uses the DPLL, the selection of TDCR/RDCR depends on the encoding/decoding. If
communication is synchronous, select 1×. FM0/FM1, Manchester, and Differential Manchester
require 8×, 16×, or 32×. If NRZ- or NRZI-encoded communication is asynchronous (that is, clock
recovery required), select 8×, 16×, or 32×. The 8× option allows highest speed, whereas the 32×
option provides the greatest resolution.
00 1× clock mode. Only NRZ or NRZI encodings/decodings are allowed.
01 8× clock mode.
10 16× clock mode. Normally chosen for UART and AppleTalk.
11 32× clock mode.
18–20 RENC Receiver decoding/transmitter encoding method. Select NRZ if DPLL is not used. RENC should
equal TENC in most applications. However, do not use this internal DPLL for Ethernet.
21–23 TENC
000 NRZ (default setting if DPLL is not used). Required for UART (synchronous or asynchronous).
001 NRZI Mark (set RINV/TINV also for NRZI space).
010 FM0 (set RINV/TINV also for FM1).
011 Reserved.
100 Manchester.
101 Reserved.
110 Differential Manchester (Differential Bi-phase-L).
111 Reserved.
24–25 DIAG Diagnostic mode.
00 Normal operation, CTS and CD are under automatic control. Data is received through RXD and
transmitted through TXD. The SCC uses modem signals to enable or disable transmission and
reception. These timings are shown in Section 20.3.5, "Controlling SCC Timing with RTS, CTS,
and CD."
01 Local loopback mode. Transmitter output is connected internally to the receiver input, while the
receiver and the transmitter operate normally. The value on RXD is ignored. If enabled, data
appears on TXD, or the parallel I/O registers can be programmed to make TXD high. RTS can
also be programmed to be disabled in the appropriate parallel I/O register. The transmitter and
receiver must share the same clock source, but separate CLKx pins can be used if connected
to the same external clock source.
If external loopback is preferred, program DIAG for normal operation and externally connect TXD
and RXD. Then, physically connect the control signals (RTS connected to CD, and CTS
grounded) or set the parallel I/O registers so CD and CTS are permanently asserted to the SCC
by configuring the associated CTS and CD pins as general-purpose I/O.
10 Automatic echo mode. The transmitter automatically resends received data bit-by-bit using the
Rx clock provided. The receiver operates normally and receives data if CD is asserted. CTS is
ignored.
11 Loopback and echo mode. Loopback and echo operation occur simultaneously. CD and CTS are
ignored. See the loopback bit description above for clocking requirements.
For TDM operation, the diagnostic mode is selected by SIxMR[SDMx]; see Section 15.5.2, "SI Mode
Registers (SIxMR)."
26 ENR Enable receive. Enables the receiver hardware state machine for this SCC.
0 The receiver is disabled and data in the Rx FIFO is lost. If ENR is cleared during reception, the
receiver aborts the current character.
1 The receiver is enabled.
ENR can be set or cleared, regardless of whether serial clocks are present. Section 20.3.7,
"Reconfiguring the SCCs," describes how to disable/enable an SCC. Note that other tools, including
the
ENTER HUNT MODE
capability to control the receiver.
20-8
Freescale Semiconductor, Inc.
and
CLOSE RXBD
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
Description
commands and the E bit of the Rx BD, data provide the
MOTOROLA